News Release from: True Circuits
Edited by the Electronicstalk Editorial Team on 22 January 2004

Low-jitter hard macro wins key timing spot

Parama Networks has implemented a True Circuits clock generator PLL as the primary clocking macro in its new ADM-on-a-Chip, fabricated in UMC's 130nm process technology.

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Parama Networks has implemented a True Circuits clock generator PLL as the primary clocking macro in its new ADM-on-a-Chip, fabricated in UMC's 130nm process technology. This chip offers system designers, for the first time on a single piece of silicon, all of the functions necessary to build add-drop multiplexers (ADMs) and other next generation network equipment. "We selected a PLL from True Circuits because of the company's PLL expertise and reputation for supplying proven PLL hard macros", remarked Kent Goodin, Vice President, VLSI Engineering, Parama Networks.

"The True Circuits 1.2GHz clock generator PLL is the core component that allows the multirate Sonet/SDH ports on the ADM-on-a-Chip to operate within the required industry jitter specifications across all supported rates".

"Our goal is to ensure our customers can easily meet their performance and timing objectives by utilising our programmable, low-jitter hard macros", remarked Dr John G Maneatis, President of True Circuits.

"These design characteristics are particularly important for the timing and performance requirements of ASICs targeting high-speed telecommunication applications like Parama's OC-192 and OC-768 ADMs".

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