Synopsys IP cores pass compliance testing

Synopsys has announced that the Designware USB 2.0 NanoPHY IP and PCI Express 1.1 PHY are the first internet protocol (IP) cores to achieve compliance in UMC's 65nm SP and LL process technologies.

Passing compliance testing is intended to help ensure interoperability and reduce risk for designers incorporating complex, high-performance interfaces into their system-on-chips (SoCs).

Synopsys provides complete IP solutions for USB 2.0 and PCI Express, consisting of digital controllers, PHY and verification IP.

The Designware USB 2.0 NanoPHY IP is designed for a range of high-volume mobile and consumer applications where the key requirements include minimal area and low dynamic and leakage power consumption.

In addition, the Designware USB 2.0 NanoPHY IP features built-in tuning circuits, which are designed to enable quick, post-silicon adjustments to account for unexpected chip/board parasitics or process variations, without having to modify the existing design.

This is said to allow designers to increase yield and minimise the cost of expensive silicon re-spins.

The Designware PHY IP for PCI Express exceeds key PCI Express 1.1 specifications in jitter, margin and receive sensitivity, thus delivering a robust design that is claimed to tolerate process, voltage and temperature variations.

Embedded high-speed mixed-signal IP, such as a PCI Express PHY, can pose significant testing challenges in terms of development time, coverage and equipment cost.

With the Designware PHY IP for PCI Express, at-speed production testing can be conducted on a pure-digital tester by using the supplied ATE test vectors for full-compliance eye-mask testing.

This is intended to eliminate the need for expensive test equipment, enabling designers to speed development time and lower costs.

Furthermore, the advanced built-in diagnostics capabilities provide customers with an on-chip sampling scope for quick debug of the SoC.

John Koeter, vice-president of marketing for the Solutions Group at Synopsys, said: 'Achieving compliance for the Designware PHY IP in popular process technologies, such as UMC 65nm, gives designers confidence that the IP being integrated will function precisely to the standard and is proven interoperable with other devices.

The Designware USB 2.0 NanoPHY and PCI Express 1.1 PHY for the UMC 65nm SP and LL process technologies are now available, according to the company.

In addition, the Designware SATA PHY, DDR2/DDR PHY and DDR 2/3 Lite PHY are also available in the UMC 65nm process technologies.

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