Product category: Design and Development Software
News Release from: Synopsys | Subject: Design Compiler Ultra
Edited by the Electronicstalk Editorial Team on 28 February 2008
Design flow lowers testing costs
The reference flow uses Design Compiler Ultra topographical technology to accurately predict post layout timing, power and area during synthesis
Synopsys and semiconductor manufacturing International have released an enhanced 90nm hierarchical, multivoltage RTL-to-GDSII reference design flow. It offers advanced synthesis, design-for-test (DFT) and design-for-manufacturing (DFM) capabilities. Key features of the reference flow include topographical synthesis in the Design Compiler Ultra product, scan compression in the DFT MAX product and critical area analysis in the IC Compiler place and route product.
This article was originally published on Electronicstalk on 28 February 2008 at 8.00am (UK)
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Together these capabilities help to lower the cost of implementing and testing systems-on-a-chip (SoCs).
'We have worked closely with Synopsys to enhance our 90nm reference flow'.
'The latest iteration builds upon the previous flow's low power consumption, DFT and DFM capabilities', said Paul Ouyang, Senior Fellow of Marketing and sales at SMIC.
Further reading
Tool suite eases chip development
The Synopsys Eclypse Low Power Solution enables design teams to adopt advanced low power techniques while boosting productivity and reducing risk
Test generator isolates small delay defects
Higher test quality enables defective parts to be identified earlier in the test process, lowering the cost of production testing
'The new flow reduces synthesis iterations and lowers test costs, providing our customers a path to significant cost savings and lower design risk'.
The enhanced reference design flow 3.2, based on SMIC's 90nm low leakage process and Synopsys' Pilot Design Environment, has been validated on Synopsys' Galaxy Design Platform with the ARM low-power design kit developed for SMIC's 90nm process.
The reference flow uses Design Compiler Ultra topographical technology to accurately predict post layout timing, power and area during synthesis, reducing costly design iterations between synthesis and layout.
Capabilities for low power design include insertion and placement optimisation of isolation cells, creation of multiple voltage areas and power meshes and synthesis of multiple voltage aware clock trees.
To help reduce standby leakage, the design flow uses power gating techniques that shut off areas of the chip when they are not needed for a function.
DFT MAX synthesises scan compression circuits that substantially lower costs by decreasing the amount of data and time required for manufacturing test.
The tool reduces the number of scan chain connections that cross voltage domains, lowering the area impact of DFT by reducing the number of required level shifters and isolation cells.
Other DFM capabilities in the flow include via optimisation and wire spreading and antenna fixing with Hercules runset.
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