Test generator isolates small delay defects

Higher test quality enables defective parts to be identified earlier in the test process, lowering the cost of production testing.

STMicroelectronics has adopted Synopsys' TetraMAX small delay defect (SDD) automatic test pattern generation (ATPG) and failure diagnostics solution to provide higher-quality manufacturing tests for its system on chip (SoC) products.

Higher test quality enables defective parts to be identified earlier in the test process, lowering the cost of production testing.

After extensive validation on manufactured designs, STMicroelectronics determined that the new TetraMAX SDD ATPG capability - which directly accesses precise timing information generated by Synopsys' PrimeTime static timing analysis solution - improved the quality of product testing by identifying unique defect classes compared with standard at speed pattern generation.

"Silicon testing on several STMicroelectronics products has proven that Synopsys' TetraMAX small delay defect patterns consistently screen more failures than the other types of test we use today in production", says Philippe Magarshack, Group Vice President, and Central CAD and Design Solutions General Manager, at STMicroelectronics.

"The step increase in test quality due to SDD test will significantly boost our DPPM reduction program, and therefore STMicroelectronics will start deployment of Synopsys' SDD ATPG by design teams in March 2008".

Small delay defects associated with nanometre processes can adversely affect timing sensitive paths in a design, leading to circuit failures under certain conditions.

Standard transition delay ATPG lacks sufficient timing resolution to create tests that reliably detect these small added delays.

The TetraMAX solution now processes precise timing information from the PrimeTime suite to generate small delay defect patterns and identify subtle defects that were previously undetectable.

The new feature is consistent with existing design for test (DFT) methodologies and does not require design changes.

"A key advantage of Synopsys' approach to timing-aware ATPG is that it leverages the PrimeTime tool", says Roberto Mattiuzzo, Digital Test Solutions Manager, Central CAD and Design Solutions, Front End Technology Manufacturing at STMicroelectronics.

"PrimeTime is widely used at STMicroelectronics for static timing analysis and sign-off because of its accurate analysis of complex timing effects".

"TetraMAX's ability to import pin slacks generated by PrimeTime to target small delay defects with very high precision is critical to improving test quality over standard transition delay ATPG".

"For years, Synopsys customers have relied on TetraMAX ATPG as a means to easily and inexpensively achieve high quality digital testing", says Antun Domic, Senior Vice President and General Manager, Synopsys Implementation Group.

"Seldom does a new ATPG technology emerge that affords customers a significant step increase in quality with no impact to the design flow".

"The new TetraMAX small delay defect ATPG capability represents just such an evolutionary improvement in quality, combined with advanced automation".

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