Product category: Design and Development Software
News Release from: Synopsys | Subject: Design Compiler Ultra
Edited by the Electronicstalk Editorial Team on 26 April 2006
Topographical technology cuts
time to market
Nvidia Corporation is using the 'topographical technology' in Design Compiler Ultra to increase the competitiveness and accelerate time to market for its next-generation designs
Nvidia Corporation is using the 'topographical technology' in Synopsys' Design Compiler Ultra to increase the competitiveness and accelerate time to market for its next-generation designs. The ability to accurately predict key characteristics of a design, such as timing and area, during the early stages of development allows Nvidia's designers to synthesise a better netlist for physical implementation.
This article was originally published on Electronicstalk on 26 April 2006 at 8.00am (UK)
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This results in significant productivity gains, fewer design iterations, and faster time to market.
'We believe Design Compiler's topographical technology is a better approach to synthesis, generating results that more closely correlate to physical implementation and therefore reduce iterations between synthesis and physical tools', said Dan Smith, Director of Hardware Engineering at Nvidia.
'The topographical technology fits readily into our design flow, delivering area and timing correlation which is within 3-6% of post-placement results'.
'In addition, with this technology we are realising reduced congestion'.
'These results, complemented by the improvements we have seen in DC Ultra 2005.09, are driving our decision to deploy this technology on our next-generation designs'.
The topographical technology in Design Compiler uses Synopsys' advanced placement and optimisation algorithms to bring accurate timing and area context into the synthesis engine, eliminating synthesis dependency on wireload models.
This results in very close timing and area correlation between synthesis and physical design, giving RTL designers early visibility into downstream design issues and eliminating costly iterations between synthesis and layout.
'The topographical technology extends Design Compiler's capabilities well beyond timing, area, power and test optimisation, making the RTL-to-GDSII design flow more predictable than ever before', said Antun Domic, Senior Vice President and General Manager, Synopsys Implementation Group.
'Market leaders like Nvidia recognise that this technology is an essential component in meeting their aggressive design goals and schedules'.
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