Product category: Design and Development Software
News Release from: Synopsys | Subject: Galaxy and Discovery
Edited by the Electronicstalk Editorial Team on 05 June 2007
Design platforms go with TSMC's flow
Synopsys is supporting the new TSMC Reference Flow 8.0 in its Galaxy Design Platform, Discovery Verification Platform and design for manufacturing (DFM) products.
Synopsys is supporting the new TSMC Reference Flow 8.0 in its Galaxy Design Platform, Discovery Verification Platform and design for manufacturing (DFM) products TSMC Reference Flow 8.0 includes statistical timing analysis for intra die variation, automated DFM hotspot fixing and new dynamic low power design methodologies
This article was originally published on Electronicstalk on 14 Oct 2003 at 8.00am (UK)
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The key components of Synopsys' Galaxy design and Discovery verification platforms are now available on Intel Itanium 2-based systems running the 64bit Linux operating system.
Tools to run faster on 64bit platforms
Synopsys is porting its Galaxy design and Discovery verification platforms to run on AMD64 architecture-based processors running the Red Hat Enterprise Linux, Version 3 operating system.
Advanced power management techniques include multi voltage and MTCMOS power gating, as well as more commonly used techniques such as clock gating and multithreshold, available through the Synopsys Galaxy Design Platform.
Reference Flow 8.0 performs comprehensive dynamic and leakage power optimisation and analysis throughout the synthesis, physical design and sign off phases of the design process.
"Our design platforms' support of TSMC Reference Flow 8.0 enables designers to address complex, deep submicron challenges", says Rich Goldman, Vice President of Strategic Market Development at Synopsys.
Further reading
Design and verification for new 90nm process
Synopsys Galaxy design and Discovery verification platforms have been verified for the new 90nm process platform common to both IBM and Chartered Semiconductor Manufacturing.
In-house design environment goes to market
The Synopsys Pilot Design Environment is a complete RTL-to-GDSII design system developed by Synopsys Professional Services and based on Synopsys' Galaxy and Discovery platforms.
Synopsis adds crosstalk analysis to timing tool
Synopsys has extended its PrimeTime static timing analysis product to address the challenge of detecting and resolving crosstalk on SoC designs at 0.18 micron and below.
"Our continued relationship with TSMC provides our mutual customers with a comprehensive, low risk solution from RTL to silicon".
The Synopsys Discovery Verification Platform enables power aware simulation, formal equivalence checking, and static analysis of designs that use advanced power management techniques such as multiple power domains, level shifters, isolation cells, and retention memory elements.
Advanced multi voltage designs have been taped out with TSMC's manufacturing technology using Synopsys power management solutions.
"Through the years, Synopsys and TSMC have worked together to meet the evolving challenges of deep submicron design", says Kuo Wu, Deputy Director of Design Service Marketing at TSMC.
"Manufacturing ease, yield, and leakage are vital design concerns at the 45nm node".
"Synopsys tools and platforms address these concerns in TSMC Reference Flow 8.0".
Reference Flow 8.0 takes advantage of new capabilities available through the Galaxy Design Platform and PrimeYield design yield analysis tool suite for 45nm readiness.
For productivity gains during implementation, designers can use concurrent yield optimisation for critical area reduction and automated hotspot fixing within IC Compiler.
For analysis, designers can now use PrimeYield LCC to perform parametric (timing) analysis in addition to functional hotspot analysis.
To enable this, the PrimeYield and Star-RCXT tools support advanced features such as Virtual CMP analysis engine.
Synopsys has worked with TSMC on a comprehensive variation aware flow that allows designers to reduce margins, improve design robustness and enhance parametric yield.
The Synopsys variation aware analysis solution consists of three important components: The Composite Current Source based statistical library, sensitivity based extraction using the Star-RCXT VX tool and statistical timing analysis technology in the PrimeTime VX tool.
With uncertainties introduced by the wide variation in device and interconnect at the sub-45nm level, customers can apply this solution to their complex 45nm system on chip (SoC) designs today.
Additional Synopsys enhancements featured in TSMC Reference Flow 8.0 include advanced design for test capabilities and support of TSMC 45nm design rules.
Reference Flow 8.0 incorporates comprehensive Synopsys based RTL to GDSII solution using the Galaxy Design Platform for RTL synthesis, physical implementation and sign off, and the Discovery Verification Platform with VCS, HSpice, and HSIM/Nanosim for RTL verification and circuit simulation.
Synopsys Professional Services provides expertise in chip implementation and flow deployment with Reference Flow 8.0.
Synopsys also distributes TSMC libraries through the DesignWare Library.
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