Product category: Design and Development Software
News Release from: Synopsys | Subject: DFT MAX
Edited by the Electronicstalk Editorial Team on 08 March 2007
Compression cuts costs of nanometre
testing
Scan compression automation results in a 90% reduction in tester related costs.
Actions Semiconductor has adopted the Synopsys DFT MAX scan compression automation solution for its 0.13um SoC designs, resulting in a 90% reduction in tester related costs DFT MAX implements scan data compression on chip to significantly reduce the amount of test time and test data required to execute high quality manufacturing tests
This article was originally published on Electronicstalk on 8 Nov 2005 at 8.00am (UK)
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