Product category: Design and Development Software
News Release from: Synopsys
Edited by the Electronicstalk Editorial Team on 22 May 2006
Design for manufacturing
tools join TSMC portfolio
TSMC has included Synopsys' integrated Design for Manufacturing tools suite in its DFM tool qualification programme for enhancing yield during design
Taiwan semiconductor manufacturing Company has included Synopsys' integrated Design for Manufacturing (DFM) tools suite in its DFM tool qualification programme for enhancing yield during design. New DFM-compliance capabilities include lithography compliance checking (LCC), critical area analysis (CAA) and CMP (chemical mechanical polishing) modelling, simulation and extraction - all integrated with design implementation.
This article was originally published on Electronicstalk on 22 May 2006 at 8.00am (UK)
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This adds to Synopsys' existing production-proven capabilities for improving manufacturability of physical design using the IC Compiler physical design solution, physical verification using the Hercules physical verification product, mask synthesis using the Proteus optical proximity correction (OPC) product, and process development and optimisation with TCAD tools.
The complete flow is critical in addressing the increasingly complex interplay between design yield and the traditional metrics of area, timing and power.
'The Synopsys DFM flow is a result of a technical relationship between the two companies to deliver on an integrated approach for tackling systematic and random yield effects', said Edward Wan, Senior Director of Design Service Marketing at TSMC.
'This decreases time to market and increases productivity and yield'.
Lithography errors are a major source of systematic yield problems.
Further reading
Acquisition addresses power management challenges
ArchPro's silicon-proven power management technologies are a natural fit with Synopsys' advanced verification platform
Measurement link aids optical proximity correction
Design for manufacturing interface helps customers to develop faster, more accurate and predictive OPC models for advanced 45nm and beyond technologies
Design platforms go with TSMC's flow
Synopsys is supporting the new TSMC Reference Flow 8.0 in its Galaxy Design Platform, Discovery Verification Platform and design for manufacturing (DFM) products
TSMC and Synopsys worked to ensure that the accuracy of Synopsys' DFM-LCC technology matches that of TSMC's production flow by flagging potential lithographical errors and process variation effects for the designer earlier in the design process.
With its advanced architecture, the DFM-LCC technology delivers fast runtimes and uses less memory for layouts ranging from library cells up to the biggest designs.
The technology also delivers superior predictability with production-quality silicon correlation from the Proteus OPC tool.
To boost designer productivity, DFM-LCC links to the leading routing tool, IC Compiler, for automated correction of lithographical errors.
Particle-induced defects are a leading cause of random yield loss.
To enable the optimisation earlier in the design flow, Synopsys and TSMC worked closely to qualify the critical area analysis (CAA) engine in IC Compiler to provide excellent correlation with the TSMC internal reference data.
IC Compiler takes a particle distribution as input and displays critical areas with higher probability of yield loss in the layout.
The tool then applies a complete wire-spreading and wire-widening methodology to reduce the average critical area and increase yield while preserving timing.
Uneven metal fill is a major source of systematic failures in advanced chip design.
The two companies validated the accuracy of DFM-CMP modelling and simulation results for full chip thickness variation analysis.
The IC Compiler tool uses the analysis results from DFM-CMP to provide model-based dummy metal filling in order to fix potential issues from metal variations caused by the CMP process.
'TSMC has a well-known reputation for providing production proven, leading-edge manufacturing flows for its many customers', said Anantha Sethuraman, Vice President of Marketing for Design for Manufacturing, Silicon Engineering Group, Synopsys.
'The selection of our tools for the TSMC DFM flow speaks to their quality, reliability, and accuracy'.
'We have worked closely with TSMC to qualify our tools for yield analysis and enhancement during and after design implementation'.
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