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Product category: Intellectual Property Cores
News Release from: Synopsys | Subject: VCS Verification Library
Edited by the Electronicstalk Editorial Team on 22 March 2006

Verification IP supports SystemVerilog development

Verification IP support for SystemVerilog provides engineers with crucial building blocks for the development of more effective testbenches to address the challenge of SoC verification

The Synopsys VCS Verification Library, containing DesignWare verification intellectual property (VIP), is first to support testbenches created using IEEE Std 1800-2005 SystemVerilog and the coverage-driven methodology defined in the 'Verification methodology manual (VMM) for SystemVerilog', published by Springer Science+Business Media.

Verification engineers who use SystemVerilog for testbench development now have access to a proven portfolio of Synopsys VIP to reduce the cost of testbench development, speed the time to reach coverage goals, and reduce risk in order to meet project schedules.

Verification IP support for SystemVerilog provides engineers with crucial building blocks for the development of more effective testbenches to address the challenge of system-on-chip (SoC) verification.

This support enables more than 600 companies that use DesignWare verification IP to adopt a coverage-based verification methodology based on SystemVerilog and the VMM for SystemVerilog.

As the standard interfaces on SoC designs continue to increase in number and complexity, verification engineers are faced with tremendous challenges.

Synopsys is leading the effort to solve these challenges with verification IP that helps simplify the creation of VMM-compliant testbenches and provides protocol-specific coverage.

When combined with Native Testbench in the VCS solution, DesignWare Verification IP delivers up to 5x improvement in verification performance.

'With a considerable increase in the verification challenge for SoCs, verification engineers are asking for proven and fully featured verification IP to reduce testbench development time and radically improve their verification productivity', said Guri Stark, Vice President of Marketing, Solutions Group, Synopsys: 'Providing a broad portfolio of verification IP with SystemVerilog support, including support for the VMM for SystemVerilog, will accelerate customer adoption of a new generation of more effective verification techniques that will increase verification coverage and significantly reduce project schedule risk'.

The VMM for SystemVerilog provides verification engineers with a robust, consistent methodology for developing testbenches that help engineers meet the challenges of verifying today's complex SoC designs.

The book defines a reusable constrained-random environment based on a coverage-driven methodology to increase verification productivity and quality.

The verification IP contained in the VCS Verification Library provides essential SoC verification building blocks for VMM-compliant environments, resulting in a significant improvement for verification productivity.

'Synopsys' broad portfolio of standards-based verification IP with support of the Verification Methodology Manual for SystemVerilog signals the growing momentum for SystemVerilog', said Janick Bergeron, Moderator of Verification Guild, co-author of the VMM for SystemVerilog and scientist at Synopsys: 'The combination of Synopsys' high-quality verification IP and the VMM for SystemVerilog is a major step toward addressing the need for a standard methodology to verify complex SoCs based on an open, industry-standard language'.

Current customers of DesignWare Verification IP can gain access to the new functionality at no additional charge by requesting the SystemVerilog version from the Synopsys website.

DesignWare Verification IP is available in the DesignWare Library, in the VCS Verification Library and as individual suites.

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