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Product category: Design and Development Software
News Release from: Synopsys | Subject: Toshiba MeP reference design flow
Edited by the Electronicstalk Editorial Team on 24 October 2003

Reference design flow
aids MeP development

Synopsys Professional Services has collaborated with Toshiba to develop the reference design flow for Toshiba's MeP media embedded processor

Synopsys Professional Services has collaborated with Toshiba to develop the reference design flow for Toshiba's MeP media embedded processor and will provide services to Toshiba's customers for deployment of the flow. The MeP is a soft (synthesisable) core with a unique configurable microprocessor architecture that can be customised for high-performance multimedia applications such as video, imaging, audio and networking.

The reference design flow enables developers to evaluate different architectural configurations of MeP in their SoC designs by more quickly and accurately estimating the resulting chip performance and size.

The reference design flow then provides an integrated path to implement the optimal configuration.

The MeP's configurability, combined with the performance and schedule predictability made possible by the reference design flow, will help ensure MeP licensees can achieve their design targets prior to silicon manufacturing and meet their market windows.

The reference design flow is based on Synopsys' best-in-class tools including, Physical Compiler and PrimeTime from Synopsys' Galaxy design platform.

This RTL-to-GDSII flow offers designers the ability to optimise their designs for performance, power, or die area, and to implement them with short turn-around times.

Toshiba provides synthesis scripts for the reference design flow optimised for the MeP architecture.

These scripts leverage Physical Compiler's RTL performance prototyping capability, which allows users to validate incoming IP against a range of physical implementations and quickly converge on an architecture that best meets their target design goals.

This leads to faster timing convergence and consequently faster time to market.

"Providing a proven reference design flow is strategic to Toshiba's business.

The MeP reference design flow developed in co-operation with Synopsys will allow our customers to meet their design goals in a short and predictable timeframe", said Tohru Furuyama, general manager, SoC Research and Development Centre, Toshiba Corp.

"Synopsys Professional Services has great breadth and depth of understanding of how SoCs are designed and verified today, including considerable experience with complex implementation and verification environments.

Our ongoing collaboration with Synopsys will enable us to achieve our goal of making the MeP core as easy to deploy as an IP library, thereby helping give our partners a time-to-market advantage".

"The reference design flow improves predictability and productivity for Toshiba's customers by creating a design environment in which they can rapidly experiment with, analyse and implement their MeP-based designs.

This is a positive step forward in automation for the configurable processor market", said John Chilton, Senior Vice President and General Manager, Solutions Group, Synopsys.

"The collaboration with Toshiba was successful not only in responding to Toshiba's specific project needs, but also in establishing a robust and repeatable design flow that can be leveraged by their customers.

We will work with our mutual customers to accelerate the deployment of their MeP-based designs".

Synthesis scripts for the MeP reference design flow will be provided through Toshiba's website.

The MeP programme provides members access to a comprehensive set of information to help them evaluate and design with MeP.

As an MeP Alliance Partner, Synopsys offers design environment support for mutual customers of Toshiba and Synopsys, including assistance with deploying and executing the MeP reference design flow for core hardening and SoC integration.

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