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Product category: Design Services
News Release from: Synopsys | Subject: Fujitsu design consulting service
Edited by the Electronicstalk Editorial Team on 30 September 2003

Consulting service to
help SoC designers

Fujitsu and Synopsys have launched a new design consulting service to help SoC designers improve the quality of designs, and thereby reduce design cycles

The companies' joint SoC design consulting service brings together Synopsys' consulting expertise in logic and physical synthesis with Fujitsu's expertise in leading-edge physical design technologies. This combination provides integrated support for customers' design processes, from the SoC specification through logic and physical synthesis to the physical design implementation stage.

The service is currently available in Japan and will gradually be expanded to other markets throughout the world.

The consulting service aims to help customers eliminate unwanted design iterations by creating a concurrent logical and physical design flow using register transfer level (RTL), netlist, and placed-gates interfaces.

This advanced engagement model gives mutual customers the ability to address key issues involving both logical and physical design from the early design planning stage, enabling a more predictable design flow that yields higher quality end-results and reduces the risk of failure inherent in many of today's high-speed, large-scale SoC designs.

As part of the service, Synopsys contributes its fundamental skills in front-end design, functional verification and physical synthesis, including the application of Physical Compiler, to help ensure that customers' designs meet specified goals for area, timing and power.

Fujitsu brings its leading-edge physical design skills such as chip image planning (floorplan) technology for early detection and control of potential back-end design problems, which are built upon its deep expertise in implementing 10-million-gate-plus SoCs.

In addition, the companies have expanded the scope of their collaborative services to support customers designing from RTL to placed-gates, providing the appropriate level of assistance to meet each customers' particular project needs.

Yoji Hino, General Manager of the ASIC, Network and Communication Products Division at Fujitsu said: "This new consulting service collaboration with Synopsys allows us to start our design support with physical aspects from the earliest stage, an important advantage that sets us apart from other solution service providers.

The resulting improvements in design estimation quality and problem prevention that we can deliver to customers, in turn, helps boost their competitive advantage by enabling them to develop chips with minimal design iterations".

"Synopsys and Fujitsu are committed to helping customers fully realise the latest advantages that our EDA and deep submicron ASIC technologies offer", said John Chilton, senior vice president and general manager of the Solutions Group at Synopsys.

"Working with customers to support their RTL or placed-gates handoff through a proven physical synthesis flow means we can help them avoid the multiple iterations that can occur between the logical and physical stages to close timing iterations that can add weeks or months to a design cycle".

Employing the new SoC design consulting service on an early-adopter basis, the High-Reliability Components Corp has already seen impressive benefits.

"We supply advanced high-quality aerospace system parts to our customers.

Enlisting the expert design services of Synopsys and Fujitsu, we were able to get our design to tapeout more quickly by avoiding the timing convergence problems encountered with a traditional netlist handoff", said Yoshihisa Tsuchiya, Senior Engineer, Engineering Department High-Reliability Components Corporation.

"Working as a team, we were confident that our design constraints were preserved from the front end of the design cycle all the way to a layout-proven netlist.

We were able to meet our performance objectives without sacrificing the predictability of our tapeout schedule".

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