Product category: Design and Development Software
News Release from: Synopsys | Subject: PrimeTime
Edited by the Electronicstalk Editorial Team on 29 April 2003
Analyser speeds to
faster timing signoff
The latest release of PrimeTime - the timing backbone in Synopsys' Galaxy design platform - has set a new standard for performance in static timing analysis and signoff of multi-million-gate designs
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Timing analyser speeds through large SoC designs
The new release of PrimeTime has set a new performance standard for static timing analysis and sign-off of 90nm designs, enabling timing analysis of 100-million gate designs
Customer benchmarks show an average of 2x and up to 7x runtime improvement over previous releases, resulting in increased designer productivity and rapid timing signoff. PrimeTime's significant performance gains are the result of algorithmic improvements to reporting and standard delay file (SDF)-based timing analysis.
"The complexity of our graphics and core logic designs has tripled over the last three years and increased our runtime demands on PrimeTime", said Wilson Wang, Director of SiS' Design Technology Development.
"With the PrimeTime 2003.03 release, we verified our latest Xabre 600 high-performance graphics chip - an eight-million gate design - in two hours, which was a 2x improvement over previous releases.
This performance gain enables our designers to achieve timing signoff in hours instead of days and meet our aggressive time-to-market goals".
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"NEC Electronics creates multi-million-gate SoC designs that require efficient timing analysis with PrimeTime", said Toshiaki Machida, Senior Manager, Design Strategy Group, 2nd System LSI Div, 2nd Business Development Operations Unit at NEC Electronics Corp.
"On a five million-gate design, PrimeTime 2003.03 completed analysis in 1 hour 15 minutes - a 3x improvement over the previous release.
PrimeTime continues to be an integral part of our design solution, accelerating the turnaround time for our complex SoCs".
"Renesas Technology Corp develops complex SoCs for mobile, network, automotive, and digital consumer applications in the ubiquitous network society", said Hisaharu Miwa, Department Manager of EDA Technology Development Dept.
in Design Technology Division, LSI Product Technology Unit at Renesas Technology Corp.
"On our latest multimillion-gate SoC with multiple clock domains and complex timing constraints, PrimeTime2003.03 delivered a 7x runtime improvement compared to the previous release.
This performance improvement enables us to speed timing sign-off of our complex designs".
As the timing backbone in Synopsys' Galaxy Design Platform, PrimeTime offers full-chip, gate-level static timing analysis together with an integrated delay calculator and advanced modelling capabilities for efficient and accurate timing signoff.
"PrimeTime continues to push the technology envelope and deliver high performance and accuracy to address customers' critical timing verification challenges", said Antun Domic, Senior Vice President and General Manager, Synopsys' Nanometre Analysis and Test business unit.
"Offered within our Galaxy Design Platform, PrimeTime now enables overnight signoff of 50-million gate designs".
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