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Product category: Design and Development Software
News Release from: Synopsys | Subject: PrimeTime
Edited by the Electronicstalk Editorial Team on 13 February 2004
Timing analyser speeds through large SoC
designs
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The new release of PrimeTime has set a new performance standard for static timing analysis and sign-off of 90nm designs, enabling timing analysis of 100-million gate designs.
The new release of PrimeTime has set a new performance standard for static timing analysis and sign-off of 90nm designs, enabling timing analysis of 100-million gate designs Customer benchmarks show an average of three times runtime improvement and up to three times data capacity improvement over the previous release
This article was originally published on Electronicstalk on 19 Apr 2001 at 8.00am (UK)