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Product category: Design and Development Software
News Release from: Synopsys | Subject: VCS 7.0
Edited by the Electronicstalk Editorial Team on 3 June 2002

Observed coverage boosts
smart SoC verification

Synopsys reckons VCS 7.0 is the first comprehensive smart verification solution to address increasing SoC verification challenges

VCS 7.0 incorporates advanced higher-abstraction verification technologies in a single open platform to enable faster verification with greater confidence. New technologies in VCS include native code generation support for OpenVera' assertions (OVA); native code generation support for OpenVera testbench constructs, called "VeraLite"; native support for CycleC, a RTL C++ performance technology; and a new native coverage metric - observed coverage.

"We have been using VCS successfully for more than ten years to verify our high performance microprocessor designs", said Sunil Joshi, vice president, Corporate CAD, Sun Microsystems.

"The evolution of VCS from a fast Verilog simulator to a highly integrated, high performance RTL verification platform is what is needed to meet Sun's demanding verification requirements".

As verification consumes up to 70% of the design cycle, engineering teams seek evolutionary solutions that improve productivity and throughput with minimal risk.

VCS 7.0 provides a Smart Verification solution that delivers higher-abstraction assertion-based verification and testbench technology, higher performance C++ modelling, and advanced coverage technology-all native to and integrated in an industry-proven HDL simulation platform.

"VCS 7.0 is a milestone release", said Manoj Gandhi, senior vice president and general manager of the Verification Technology Group at Synopsys.

"We have a strong track record of delivering innovative verification technologies to help our customers.

By incorporating these technologies in VCS 7.0, we have evolved VCS and redefined simulation".

Higher-abstraction verification enables increased performance and productivity VCS 7.0 delivers native support for OVA, which provides higher-abstraction for modelling assertions.

This enables design engineers to easily leverage the power of assertion-driven verification within VCS and provides high performance and productivity.

OVA allows smart use of simulation cycles by constantly monitoring and checking design behaviour during simulation, enabling designers to achieve higher verification productivity.

"VCS with OpenVera assertions accelerates implementation of our verification environment four times faster than Verilog assertions", said George Apostol, vice president of Silicon Engineering, BRECIS Communications, leading developer of Multi-Service Processors for routers, security appliances and multiservice gateways.

"Within days, we were able to write OpenVera assertions and use them to find functional bugs.

Using VCS, we can easily reuse these assertions throughout the verification flow from block-level through chip-level".

Creating testbenches to verify designs requires comprehensive data structures and powerful language constructs.

VeraLite is a subset of OpenVera testbench language natively supported in VCS that enables users to write tests at a higher level of abstraction compared to Verilog.

VeraLite augments Verilog design verification with easy-to-use, powerful constructs that allow verification-specific tasks such as real-time self-checking, advanced flow control, advanced multi-threading, and inter-thread communication.

VeraLite significantly improves verification productivity and performance due to native code generation support within VCS.

"Native support for OpenVera in VCS with VeraLite is an excellent step in raising the verification productivity of the Verilog design community".

said Janick Bergeron, CTO, Qualis Design.

"With VeraLite, designers will have access to OpenVera testbench constructs that provide higher-levels of abstraction within their familiar Verilog environments".

VCS 7.0 extends its built-in comprehensive coverage technologies with advanced observed coverage metrics (OBC) to provide new insight into test quality and smart guidance to the designers for improving tests and finding bugs.

OBC provides feedback above and beyond traditional coverage technologies by reporting that tests not only exercise the design, but also generate observable activity on user-specified outputs.

This new metric enables design teams to improve the quality and completeness of verification tests and increase their confidence in their verification environments.

"We use VCS extensively for the verification of our industry-leading high-performance, low-power embedded RISC cores", said Bryan Dickman, CPU Design Verification Manager, ARM.

"With comprehensive coverage technology in VCS we expect to enhance our verification effectiveness due to the performance advantage that this built-in capability provides".

"Meeting our customers' quality requirements for our configurable microprocessor IP is essential to our success", said Kaushik Sheth, chief engineer at Tensilica.

"To achieve our quality goals, we have added VCS observed coverage to our verification methodology.

By using observed coverage, we can produce higher quality designs than we could using only traditional coverage tools".

VCS CycleC C++ coding style enables up to 10 times performance improvement over HDL simulation for synchronous RTL designs.

VCS 7.0 provides the technologies for design teams to easily develop CycleC models and integrate them into the VCS simulation engine.

These technologies include a CycleC style checker to ensure C++ models adhere to CycleC coding guidelines; automated integration of CycleC models into VCS via the DirectC interface; and a utility to translate CycleC models to Verilog RTL for use within a standard implementation flow.

VCS 7.0 will be available in Q4, 2002.

Pricing starts at $20,250 for a one-year technology subscription license (TSL).

Customers on maintenance will have access to all VCS 7.0 smart verification technologies at no additional cost.

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