Product category: Design and Development Software
News Release from: Synopsys | Subject: Formality 2002
Edited by the Electronicstalk Editorial Team on 19 March 2002
Formal verification solution
cuts setup and debug
New from Synopsys, Formality 2002 is a next-generation equivalence checker that addresses the need for an easy-to-use formal verification solution
Formality's new flow-based graphical user interface guides the user through the equivalence checking process, reducing the time associated with setup and debug. A new simplified design read flow helps trim costly iterations in the equivalence checking process. Users can seamlessly import simulation scripts with the new simulation-style design read to ensure the right setup the first time.
This article was originally published on Electronicstalk on 19 March 2002 at 8.00am (UK)
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With Formality 2002, customers gain time-to-market advantages by reducing the time spent at every step of the equivalence checking process.
The benefits of increased productivity and reduced risk of a silicon respin have made equivalence checking a mandatory component of today's verification.
By matching the engineer's thought process, Formality 2002's new flow-based GUI provides immediate out-of-the-box productivity.
"Nvidia and Formality have enjoyed great success over the last couple of years", says Chris Malachowsky, cofounder and vice president of engineering at Nvidia.
"Synopsys' Formality technology has become a must-have in our verification strategy.
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To achieve widespread deployment, an equivalence-checking tool must be easy to use without compromising coverage, and Formality 2002 meets the requirement.
Synopsys' leadership in performance and capacity enables us to routinely verify 10-million-gate designs".
"We have not had a single chip failure because of implementation errors since adopting Formality almost three years ago, " says Kazumasa Doi, senior engineer, Fujitsu Digital Technology.
"Formality enables us to find implementation errors quickly and easily.
Thanks to Formality we deliver products early to the market and we maintain the highest level of product quality.
With Formality in our flow, we have successfully taped out roughly 60 telecomms chips of increasing complexity".
A formal verification tool needs to identify errors quickly, but this is only the first half of the engineer's challenge.
The bigger, more time-consuming challenge is debugging the cause, or source, of the error.
Formality 2002 features advanced graphical debug capabilities - such as an integrated HDL source browser and automated hierarchical scripting - to help speed error isolation and resolution.
A pattern display window enables engineers to view all failing inputs so that they may choose and apply the most appropriate pattern for debugging.
"Formality 2002 offers the first flow-based equivalence checking environment in the market aimed at assisting all engineers through the verification process", said Antun Domic, senior vice president and general manager of Synopsys' Nanometer Analysis and Test Group.
"This latest release of Formality includes the enhancements our customers require to meet their design verification and time-to-market challenges.
We will continue to work closely with customer design teams to ensure their success".
Formality 2002 will be available end of March 2002 as part of the Synopsys 2002.03 release.
Current Formality customers will receive the upgrade at no additional charge.
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