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Product category: Design and Development Software
News Release from: Synopsys | Subject: VCS 6.1 and Scirocco 2001.10
Edited by the Electronicstalk Editorial Team on 26 February 2002

Triple the performance
from latest simulators

Synopsys has unveiled the latest releases of its VCS Verilog simulator, VCS 6.1, and its high-performance Scirocco VHDL simulator, Scirocco 2001.10

Customer designs using these new releases show register transfer-level and gate-level simulation performance improvements of up to three times over previous versions, while also showing a reduction in memory consumption of up to 30% for Verilog designs. Furthermore, new crosscompile technology incorporated in the 64bit version of VCS additionally increases capacity for Verilog designs.

Leveraging this technology, customers have simulated designs in excess of 20 million gates within their existing verification environments.

"We are using VCS 6.1 on our microprocessor designs and we are seeing performance increases compared to earlier versions", said Sunil Joshi, vice president of design automation and compute resources group, Sun Microsystems.

"Our long-running relationship with Synopsys has also produced several benefits for mutual customers, such as the increased capacity with VCS' 64bit compile mode".

To allow customers to take immediate advantage of VCS 64bit support, Synopsys has developed a novel simulation crosscompile technology.

Crosscompiling allows customers to compile large designs on 64bit servers, and then simulate the designs using 32bit workstations.

Using this flow, customers can take advantage of their 64bit machines' capacity for the one-time, memory-intensive compile step while enabling engineers to use their existing hardware and Verilog PLI-based software investments for simulation.

"Many of our customers have both Denali MMAV verification IP and VCS integrated into their verification environments", said Kevin Silver, vice president of marketing at Denali Software.

"We have tested the new VCS 64bit crosscompile technology and are excited to see that it is fully compatible with our existing 32bit products, allowing our customers to maintain their existing flows without any modifications or product updates".

VCS 6.1 supports the latest language standard Verilog 2001, including the latest Verilog Programming Language Interface (PLI) and its enhanced Verilog Programing Interface (VPI) library.

VCS and Synopsys Design Compiler interpret the Verilog 2001 standard consistently, providing users with a seamless Verilog design and verification flow The latest release of Scirocco VHDL simulator, version 2001.10, has improved "out-of-the-box" event-based performance up to three times without user intervention.

Other improvements include expanded cycle-based performance for both non-RTL blocks and memories described with the VHDL ASIC library design standard known as Vital.

When combined with VCS 6.1, these performance improvements in Scirocco enable up to three times faster mixed-HDL simulation over previous versions.

"As design sizes and complexity increase, verification continues to be a significant bottleneck for Verilog, VHDL and mixed-HDL designs", said Manoj Gandhi, senior vice president and general manager of the verification technology group at Synopsys.

"Our innovative R and D efforts have again extended the performance and capacity envelope of our leading VCS and Scirocco simulators to keep pace with our customers' demanding verification schedules".

Pricing for VCS and pricing for Scirocco both start at $20,250 for a one-year technology subscription license (TSL).

Pricing for the VCS MX package for mixed-HDL simulation starts at $31,500 for a one year TSL.

Customers who own both VCS and Scirocco have immediate access to mixed-HDL simulation at no additional charge.

All products are immediately available.

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