Product category: Programmable Logic Devices
News Release from: STMicroelectronics | Subject: SPEAr Basic
Edited by the Electronicstalk Editorial Team on 27 May 2008
Configurable SoC speeds custom devices
to market
The SPEAr Basic integrates an advanced ARM926EJ-S processor core with two memory caches and up to 300,000 gates of embedded configurable logic.
STMicroelectronics has added a new member to its SPEAr family of configurable system-on-chip ICs Manufactured in state-of-the-art low-power 65nm process technology, the new SPEAr Basic device addresses a wide variety of embedded applications, including entry-level printers, fax machines, digital photo frames, voice-over-IP and other equipment
This article was originally published on Electronicstalk on 8 Nov 2004 at 8.00am (UK)
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ST's SPEAr (structured processor enhanced architecture) concept uniquely combines cost savings and shorter time to market of open-market standard products with the flexibility of application-specific ICs in optimising system performance.
Transfer of the SPEAr family to 65nm process technology yields increased density, performance and power-reduction features in new SPEAr devices.
ST's newest configurable SoC integrates an advanced ARM926EJ-S processor core with two memory caches, running at 333MHz, for data and instructions and up to 300,000 gates (ASIC-equivalent) of embedded configurable logic.
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The new SPEAr Basic provides memory interfaces supporting LP-DDR and DDR2 memories and a large connectivity IP (intellectual property) portfolio, including Fast-IrDA interface, Ethernet MAC, three USB 2.0 ports with embedded PHYs, UART, SPI, I2C, up to 102 fully programmable GPIOs and a total of 72Kbyte of SRAM and 32Kbyte of boot ROM.
Best-in-class printing performance is enabled through a full set of image-pipeline accelerators, from colour-space conversion to raster-file generation, a rotation engine, a hardware JPEG codec, an LCD controller (up to 1024 x 768, 24bit per pixel) and a SDIO/MM card interface.
Additional features include a 10bit A/D convertor, a crypto accelerator based on ST's proprietary C3 IP, a flexible static memory controller (NOR/NAND Flash and SRAM), TDM (time-division multiplexing) and SLIC (serial link and interrupt) controllers and a camera interface, providing unprecedented scale of integration and flexibility.
The SPEAr Basic's software-configurable power-saving modes address most recent ecological and power-sensitive specifications.
The device supports most popular embedded operating systems including Linux, VxWorks, ThreadX and Windows CE.
The SPEAr Basic comes complete with an evaluation board that allows quick and easy setup, design and testing of the devices.
Using the SPEAr Plus600 development kit and its external FPGA, which mirrors the SoC's internal configurable logic block, designers can proceed with software and hardware development without waiting for final validation.
Once the customer's SoC passes the functional qualification, full production can typically ramp up in eight to ten weeks from the final RTL availability.
"Leveraging ST's market-leading configurable SoC architecture, the SPEAr Basic provides a seamless cost-reduction path for applications where price/performance is key", said Loris Valenti, General Manager of ST's Computer Systems Division, Computer Peripherals Group.
"The new SPEAr device speeds the adoption of customised 65nm IC solutions with an ASIC-like flexibility, at a fraction of the development time and cost required by a full-custom design approach".
"In addition, customers can easily re-use software developed for previous SPEAr family members".
"All this makes the SPEAr Basic the best time to market solution for a variety of slots, with no compromise in features and performance".
Samples are available now, with volume production set to start by the end of Q3 2008.
The SPEAr Basic is priced at US $6, in quantities above 20,000 pieces.
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