Serdes chipset claims lowest output jitter

Chipset serialises data up to 3.125Gbit/s and is well suited for industrial and medical imaging, communications infrastructure, commercial displays, and test and measurement systems.

National Semiconductor reckons its latest serialiser and deserialiser (serdes) chipset delivers the industry's best output jitter performance of 35ps peak-to-peak and the best input jitter tolerance of 0.9 units interval (UI) with a bit error rate (BER) of 10e-15.

The serdes chipset serialises data up to 3.125Gbit/s and is well suited for industrial and medical imaging, communications infrastructure, commercial displays, and test and measurement systems.

The highly integrated chipset includes the DS32ELX0421 serialiser and DS32ELX0124 deserialiser.

They feature advanced on-chip signal and clock conditioning circuitry that extends data transmission reach of Cat6 (shielded 23 AWG) cable beyond 20m.

The serdes also support a wide variety of interconnect media, including Cat5 cable, optical fibre, 50 or 75ohm coaxial cable and FR-4 backplanes.

The serdes' unique architecture replaces the traditional wide single-ended parallel bus with a 5bit low-voltage differential signalling (LVDS) interface.

This breakthrough interface simplifies board layout by reducing the number of input/output (I/O) pins and traces between the serialiser, deserialiser and field-programmable gate array (FPGA).

In addition, the serdes' LVDS interface reduces electromagnetic interference (EMI), while enabling the use of low-cost FPGAs in a variety of high-speed, high-performance applications.

The serdes' redundant I/Os and retimed active loop-through enable advanced system configurations such as failover, link aggregation and daisychaining.

Power consumption is less than 1W, and both devices include an automatic standby mode using signal detect and a configurable sleep mode for additional power savings.

"National's new family of high-speed serialisers and deserialisers is optimised to serve as a front-end chipset to our low-cost Spartan-3 Generation FPGA products", says Oliver Garreau, Senior Engineering Manager in the Spartan FPGA Group at Xilinx.

"This serdes solution supports a broad array of high-speed applications with excellent analogue performance, while remaining cost-effective thanks to a high level of integration".

"Low cost FPGA families have lacked the ability to support high speed serial interfaces", says Jim Beneke, Vice President of Global Technical Marketing for Avnet Electronics Marketing.

"With the introduction of National Semiconductor's new serialisers and deserialisers, our customers now have the ability to add high speed serial interfaces that are both easy to implement and cost effective".

"Together National and Avnet have developed the necessary tools and reference designs to help our FPGA customers succeed in using these exciting new serdes products".

National also offers reference IP and design guides for interfacing FPGAs to the DS32ELX0421 and DS32ELX0124.

As part of its FPGA IP package, National includes a bit error rate test (BERT) engine for test pattern generation/validation and system-level functions such as link aggregation and failover.

Offered in a small 48-pin LLP package, National's DS32ELX0421 serialiser includes a double datarate (DDR) 5bit LVDS parallel data interface and a redundant serial output channel.

The integrated jitter cleaning PLL accepts a wide 125 to 312.5MHz input clock for a serial datarate of 1.25 to 3.125Gbit/s.

The DS32ELX0421 allows programming of transmit de-emphasis levels, output voltage levels, and selection of DC-balance encoding.

This programming flexibility enables the use of DS32ELX0421 in a wider range of interconnect media and applications compared with existing serialisers.

A remote sensing feature automatically detects and negotiates link status with the companion DS32ELX0124 deserialiser.

The DS32ELX0421 typically consumes 470mW of power at 3.125Gbit/s.

Offered in a small 48-pin LLP package, National's DS32ELX0124 deserialiser includes a DDR 5bit LVDS parallel interface, redundant serial input and retimed serial output channel.

The DS32ELX0124 deserialises up to 3.125Gbit/s of high-speed serial data to five LVDS outputs without the need for an external reference clock.

The DS32ELX0124 offers programmable receive equalisation, and a minimum jitter tolerance of 0.9UI.

A remote sensing feature automatically signals link status conditions to its companion DS32ELX0421 serialiser for intelligent link management.

The DS32ELX0124 typically consumes 525mW of power at 3.125Gbit/s.

In addition to the DS32ELX0421 serialiser and DS32ELX0124 deserialiser, National also offers the DS32EL0421 serialiser for applications that do not require a redundant serial output channel and the DS32EL0124 deserialiser without a redundant serial input and a retimed serial output channel.

Available now, the DS32ELX0421 serialiser and DS32ELX0124 deserialiser are priced at US $18 each in 1000-unit quantities.

Also available now, the DS32EL0421 serialiser without redundant output channel and the DS32EL0124 deserialiser without redundant input and retimed output channel are US $14 each in 1000-unit quantities.

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