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Product category: Analogue and Mixed Signal ICs
News Release from: National Semiconductor | Subject: LMK03000 etc
Edited by the Electronicstalk Editorial Team on 16 November 2006

Clock conditioners claim best jitter
performance

Precision clock conditioners integrate all the functions required to clean and distribute ultra-low-noise clock signals throughout a system.

National Semiconductor has introduced a family of five precision clock conditioners that integrate all the functions required to clean and distribute ultra-low noise clock signals throughout a system Featuring National's phase locked loop (PLL), voltage controlled oscillator (VCO), and high-speed interface technology, these clock conditioners deliver the industry's best jitter performance, making them well-suited for accurate clocking in high performance data conversion and data processing subsystems

The new family has been demonstrated this week clocking National's new analogue-to-digital convertors on Booth 506 in Hall A4, at the Electronica trade show in Munich, Germany.

The demonstrations highlight wireless and wired infrastructure, medical, and test and measurement applications as three of the key equipment markets for the clock conditioners.

National's new LMK03000, LMK03000C, LMK03001, LMK03001C and LMK02000 clock conditioners integrate a high-frequency PLL, an ultra-low-noise VCO and programmable low noise outputs.

The clock conditioners deliver typical jitter performance as low as 0.2ps, the lowest in the industry from a single chip.

Until today, system designers used expensive multiple-chip VCXOs or clock modules to achieve low jitter.

National's new single chip clock conditioners significantly reduce the system cost and save board space, power and design time.

In addition, the clock conditioners create eight frequency-and skew- programmable copies of the conditioned clock, eliminating the cost, jitter and space associated with external clock distribution components.

This feature enables clocking complex systems that require multiple clock frequencies for different functional blocks.

National's clock conditioner family is available in three pin-compatible performance grades, allowing flexible system design performance evolution using one PC board layout.

National fabricates the clock conditioner family on its proprietary BiCMOS8 process technology in its South Portland, Maine, facility.

This state-of-the-art silicon germanium process enables the devices to achieve the lowest jitter and power performance in the industry.

National's new precision clock conditioners deliver jitter performance as low as 0.2ps from a noisy 1 to 200MHz input clock.

They feature a high-performance integer-N PLL core, an integrated VCO, and three LVDS plus five LVPECL clock outputs.

The LMK03000C and LMK03001C each feature jitter performance at 0.4ps RMS and the LMK03000 and LMK03001 feature jitter performance at 0.8ps RMS.

The new LMK02000 clock conditioner features a PLL core that connects to an external voltage controlled crystal oscillator (VCXO) for even lower jitter at 0.2ps RMS.

National's new clock conditioning devices are offered in a small 48-pin LLP package and are footprint-compatible with each other to allow the system designer to easily scale up or down in jitter performance without changing the PC board layout.

Each of the eight clock conditioner outputs incorporates a low-noise clock distribution channel including a dedicated programmable divider, a phase synchronisation circuit, a programmable delay block and an LVDS or LVPECL clock output buffer.

The system designer programs each clock output divider and delay circuit individually to create multiple integer-related, but phase-adjusted copies up to 785MHz frequency, with output skew adjustable from 0 to 2.25ns in 150ps steps.

National's clock conditioners also allow the system designer to place all clock outputs into a high impedance state via the global output enable (GOE) pin.

The designer can connect the GOE to the chip's lock detect (LD) output to automatically disable all the outputs when a valid input clock is not present.

In addition, the designer can individually place unused outputs into high impedance.

When using multiple clock conditioners, the devices provide a synchronisation input pin to easily synchronise multiple clock conditioner devices on start-up.

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