Full-chip verification includes power simulation

Lexsim from Nassda Corp is a full-chip circuit-level simulator designed for post-layout verification of large integrated circuits and their associated power networks.

Lexsim from Nassda Corp is a full-chip circuit-level simulator designed for post-layout verification of large integrated circuits and their associated power networks.

Lexsim is the first EDA tool able to simulate the nanometer effects of both the power network and signal interconnects for complex ICs with millions of transistors.

By enabling semiconductor designers to identify and correct nanometer design problems during verification, Lexsim can help create chips that work successfully at first silicon.

Early silicon success provides a significant competitive advantage to semiconductor companies by reducing time to market and permitting a faster ramp to volume production.

"As leading IC manufacturers move to advanced nanometer technologies, they find that traditional simulation tools cannot uncover complex nanometer effects such as dynamic voltage (IR) drop in the power network", said Simon Young, Product Line Manager at Nassda.

"With its efficient annotation of post-layout parasitics, we believe that Lexsim provides the speed, capacity and accuracy needed for complete full-chip transistor-level circuit simulation including power-nets, and that it enables designers to find and correct critical nanometer design problems prior to manufacturing".

Matsushita Electric has added Lexsim to its memory design flow.

"Being able to more accurately predict the behaviour of our large embedded memory designs requires the inclusion of the effect of IR drops in the power networks", said Hiroyuki Tsujikawa, Manager, Matsushita's EDA Technology Development Group.

"With smaller nanometer geometries and finer metallisation, in combination with the higher currents at lower Vdds, we see the need for detailed power-net analysis to prevent possible dynamic IR drop caused design failures.

Lexsim has demonstrated the ability to simulate our full-chip at the post-layout stage including both signal-net and power-net parasitics.

We expect to see reduced design turns and faster time-to-volume by using Lexsim".

IR drop is a supply voltage reduction across a large IC as current flows through its power grid.

Reduced voltage supply to internal transistor circuitry causes increased signal delay and sensitivity to noise, which can drastically affect circuit behaviour.

In older manufacturing technologies, with supply voltages above 3V, IR drop had a negligible effect on circuit performance.

However, with the emergence of nanometer technologies of 130nm and below, a smaller supply voltage in the range of 1 to 1.5V is used and designs are more sensitive to voltage variations.

Reduced voltage supply in combination with a persistent device threshold level, results in diminished headroom for asserting logic values which can be severely affected by IR drop.

Today IR drop can significantly change timing in critical circuit paths and cause complex malfunctions that lead to frequent failure of nanometer ICs.

In the past, companies discovered IR drop problems most often after manufactured silicon failed to function as expected.

Indeed, designs can pass verification checks with traditional EDA tools but sometimes fail in actual silicon because dynamic IR drop effects were not addressed.

In diagnosing and correcting IR drop, companies have faced significant delays and additional costs associated with redesign efforts and silicon respins.

Accurate prediction of dynamic IR drop is possible only with transistor-level circuit simulation of the entire design including both power and ground networks.

Earlier transistor-level tools such as Spice and its "fast Spice" derivatives lack the performance and capacity to deal with large post-layout netlists which include a huge amount of power network parasitic data.

Post-layout netlists can be tens of gigabytes in size due to parasitic resistance and capacitance elements that exceed the capacity limit of traditional tools.

Lexsim employs sophisticated techniques to reduce power network parasitics to manageable levels with only a slight degradation in the accuracy of analysis.

In addition, Lexsim has a unique capability that incorporates signal interconnect parasitics extracted from the post-layout design stage on to the pre-layout design netlist.

Lexsim is especially efficient at simulating the effects of coupling capacitance on signal nets which include glitch power, noise, and crosstalk delay.

This combination of power-net reduction and parasitic annotation enables Lexsim to provide the highest capacity and speed needed for effective post-layout simulation of large ICs.

As a result, Lexsim is able to perform direct analysis of dynamic IR drop, unlike earlier methods that provide only static analysis or indirect approaches for circuits of limited size.

Results from Lexsim allow designers to observe dynamic IR drop effects on circuit behaviour and then to focus on any specific circuit modifications needed to correct IR drop problems.

Lexsim's ability to predict problems due to IR drop at the post-layout stage helps reduce design turns and get semiconductor products to market faster.

The initial release of Lexsim is targeted for full-chip post-layout verification of large IC memories and embedded memory intellectual property.

Future releases will address SoC and large mixed-signal designs.

"Nassda's unique technologies for power net reduction and parasitic annotation offer critical capabilities which are needed by the IC industry as it moves to nanometer design", said An-Chang Deng, Nassda's president and chief operation officer.

"We believe that Lexsim's full-chip dynamic IR drop analysis meets the important verification challenge of the latest nanometer designs and will help designers achieve improved product quality and early silicon success".

Lexsim is available immediately directly from Nassda.

Pricing for time-based licenses starts from $180,000.

Lexsim is supported on Sun Solaris, HP-UX, Windows NT/2000 and Linux platforms.

(This was Electronicstalk's Top Story on 7 May 2002).

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