Analysis overcomes nanometre design challenge

The latest version of HSIM analyses circuit behaviour while taking into account the electrical and parasitic effects of nanometre-scale silicon for analogue, mixed-signal, memory and SoC designs.

The latest version of HSIM from Nassda analyses circuit behaviour while taking into account the electrical and parasitic effects of nanometre-scale silicon for analogue, mixed-signal, memory and SoC designs.

Version 2.0 delivers new debug and analysis capabilities along with new device model support.

"Nassda's HSIM version 2.0 further enhances the accuracy and nanometre analysis we offer to designers", said Sang Wang, CEO of Nassda.

"Over 100 customers are using our technology in their analog, mixed-signal, memory and SoC design flows.

We believe this confirms that we offer a necessary verification platform for nanometre design teams to be successful.

We expect our technology will become even more widely adopted by the design community as they move to geometries at 180nm and below where the challenges of nanometre design become more difficult".

With version 2.0, HSIM adds several important capabilities including IDDQ power leakage analysis and a new design debugging option, called CircuitCheck, which identifies circuit problems early in design.

The new release also includes three additional methods of analysis Monte Carlo, AC frequency and DC sweep as well as an expanded set of supported MOS and bipolar device models and an enhanced netlist back-annotation feature.

The additional HSIM capabilities are designed to meet evolving needs for nanometre verification.

"We believe Nassda's HSIM version 2.0 further strengthens our leadership in nanometre circuit verification with the addition of new analyses and models", stated Dr An-Chang Deng, President of Nassda.

"HSIM's new power leakage analysis is very important to low power designers who are looking to deliver the best designs with the lowest power budget.

With our new CircuitCheck option, designers can enjoy faster debug times and catch circuit design problems earlier.

We have also added Monte Carlo statistical analysis so designers can better understand and improve the manufacturability of their designs.

Nassda continues to meet the nanometre design challenges of companies throughout the world".

Creating low-power designs is a key requirement for portable electronics.

An important component of power consumption is the steady-state, or IDDQ leakage current, in CMOS IC designs.

As companies move to smaller geometries at or below 180nm, this leakage current rises dramatically.

Before HSIM version 2.0, designers were typically unable to conduct accurate full-chip analysis of IDDQ because designs exceeded the capacity of their existing tools.

Now designers of low-power memories and IP are provided the capability to verify that their designs will be within their steady-state power budgets before committing to tapeout.

Available for purchase as an option to HSIM version 2.0, CircuitCheck screens, identifies, and reports potential netlist and circuit design problems before designers begin lengthy analyses of designs.

By using CircuitCheck, designers can also speed up the debugging process of simulation failures reported by HSIM.

CircuitCheck provides sophisticated static analyses to report signals with excessive rise or fall delays and potential signal nets susceptible to crosstalk noise.

CircuitCheck is used before simulation to detect design data and potential usage problems such as uninitialised latches and during simulation to monitor devices for incorrect or undesirable operating conditions.

Advanced debug features include the automatic detection of sources that trigger changes in outputs.

CircuitCheck can save design teams days to weeks of debug time.

With version 2.0, HSIM now provides three new analyses that are needed by analogue designers and library and IP developers.

Monte Carlo statistical analysis allows the investigation of how component variation affects the performance and manufacturability of designs.

With Monte Carlo analysis, designers can verify whether their designs will be successful despite small changes in component values due to manufacturing fluctuations.

AC frequency analysis is now available for designs where analogue signal processing and conditioning need to be studied.

Lastly, DC sweep analysis provides for creating a series of runs based on changing parameter values for selected components in a design and is used for investigation of various operating conditions.

These new analyses are compatible with existing Spice simulators, giving analogue designers and library and IP developers the ability to use these familiar capabilities in HSIM.

Nassda's HSIM has expanded its set of supported MOS and bipolar device models to meet the demands for higher accuracy analysis in smaller nanometre geometries and at radio frequencies.

The latest MOS device model from UC Berkeley for nanometre-scale devices, BSIM4.2, is now supported.

The Semiconductor Technology Academic Research Center (STARC) of Japan HiSIM MOS model is also supported.

Customer-proprietary device models such as Motorola's SSI MOS and the Philips MOS 9 and MOS 11 model types have also been added.

For bipolar models, HSIM now supports VBIC1.2 and the new Philips Mextram 504 model.

With each new release, HSIM intends to incorporate the latest developments from industry and academic research.

HSIM version 2.0 provides support for the back-annotation of parasitic RC data in SPEF format including coupling capacitors for crosstalk noise analysis.

Since it accounts for post-layout effects, back-annotation of parasitic data is necessary for accurate analysis of signal integrity, timing and power behaviour.

Nassda reckons HSIM tackles the critical issue of analysing circuit behaviour while taking into account the electrical and parasitic effects of nanometre-scale silicon.

Before the availability of HSIM, design teams were unable to analyse these effects with a tool that had the necessary speed, accuracy, and capacity.

In a recent benchmark at Mitsubishi Electric, HSIM verified a 512Mbit DRAM, with over 2 billion circuit elements, in less than 6h on a 32bit workstation.

HSIM's ability to address critical verification issues is reflected in the rate of adoption by design teams throughout the world.

Nassda created HSIM to perform full-chip circuit simulation and analysis of VLSI designs with accuracy within 0-2% of Spice but at speeds three to four orders of magnitude faster than Spice.

HSIM uses a patent-pending hierarchical technology and targets both pre- and post-layout analysis of circuits.

HSIM Version 2.0 is available in April 2002, and is supported on workstations running Sun Solaris, HP-UX 10.2 and 11, Microsoft Windows NT/2000, and Linux operating systems.

Customers under maintenance receive HSIM version 2.0 at no charge.

US time-based list prices start at $85,000 for HSIM.

The CircuitCheck option to HSIM version 2.0 is now available for purchase.

The CircuitCheck US time-based list price is $42,000.

(This was Electronicstalk's Top Story on 27 February 2002).

(This was Electronicstalk's Top Story on 27 February 2002).

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