Product category: Design and Development Hardware
News Release from: Mentor Graphics UK | Subject: SpeedGate DSV
Edited by the Electronicstalk Editorial Team on 26 August 2002
FPGAs provide direct
verification for ASICs
SpeedGate DSV (Direct System Verification) uses off-the-shelf FPGAs to create ASIC prototypes that can be tested at speeds comparable to a real-time operating environment
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FPGA prototyping speeds SoC verification
SpeedGate DSV (Direct System Verification) is an advanced verification environment for creating ASIC and SoC prototypes using off-the-shelf FPGAs
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Mentor Graphics has validated its Calibre LFD (litho-friendly design) results in silicon on 65nm process technology
Version 2.0 adds distributed processing interfaces to accelerate compute-intensive operations, such as synthesis and place and route, driving down costs by reducing the time for those steps in direct relation to the amount of compute farm resources used. The new version also expands language support to include Verilog, VHDL and mixed-HDL.
"The SpeedGate DSV tool is extremely popular with our customers because it offers advanced ASIC verification features, from design to prototype", said Harish Balan, product marketing manager, SpeedGate DSV, Mentor Graphics.
"With version 2.0 Mentor Graphics has accelerated the verification cycle further by adding load-sharing capabilities that allow designers to concurrently perform compute-intensive tasks that until now have consumed much of the total verification time".
The SpeedGate DSV 2.0 product includes integrated support for Platform Computing's LSF (load sharing facility) and Sun Microsystems Grid Engine, allowing designers to distribute compute-intensive operations, such as synthesis, across clusters of workstations.
Direct interfaces to load-sharing tools allow parallel submission of synthesis jobs for faster, complete module synthesis.
The technology can also extend to speed up place and route processing.
Further reading
Mixed-signal flow is proved with UWB transceiver
Mentor Graphics has set up a new reference flow for analogue and mixed-signal SoC designs
Functional verification expands in scope
Platform addresses low-power verification and incorporates verification management capabilities that enable closed-loop management reporting, analysis and documentation
500 companies download datatypes
Mentor Graphics' Algorithmic C (AC) datatypes enable algorithm, system and hardware designers to precisely model bit-true behaviour in C++ specifications while accelerating simulation speeds
Software creates user interfaces for new devices
API delivers a new approach for rapid creation of dynamic user interfaces for electronic devices, enabling manufacturers to deliver visually appealing and easy-to-use electronic-device UI screens
Faster synthesis and place and route operations lead to faster prototype development and a significant reduction in total verification time.
"Platform Computing works closely with Mentor Graphics to provide integrated solutions that maximise productivity and accelerate time-to-market for designers", said Paul Hill, vice president, marketing and business development, Platform Computing.
"With our distributed software solutions, complex tasks can be shared across multiple workstations, shrinking verification times significantly and ensuring productivity in a complex and competitive industry".
SpeedGate DSV 2.0 now supports Verilog, VHDL and mixed-HDL designs, enabling design teams to prototype all types of designs.
The input HDL is read into the SpeedGate DSV 2.0 partitioning technology that works on a unified database.
The design is then decomposed into its individual logic blocks and can then be effectively partitioned across multiple FPGA devices through unconstrained manipulation of the design hierarchy.
The SpeedGate DSV tool is the most comprehensive and extensible solution for all aspects for the prototype design flow - partitioning, debug and interconnect, also linking to board creation and analysis tools.
An interactive design cockpit launches partitioning and synthesis tools, and the completely scriptable interface plugs into any ASIC design environment - working hand-in-hand with emulation and gate-level simulation.
The SpeedGate DSV tool includes patent pending advanced partitioning technology that enables designers to minimise the number of FPGAs used to prototype a design.
The SpeedGate DSV tool fully supports the prototyping process with a team design environment, including sophisticated check-in/check-out features that track source code changes and manage version control.
SpeedGate DSV 2.0 is available now at a price of $98,500 for a floating license; the upgrade from SpeedGate DSV 1.0 is free to existing customers.
SpeedGate DSV supports Sun Solaris 2.7 and 2.8 and supports ASIC partitioning to Xilinx FPGAs.
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