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Product category: Design and Development Software
News Release from: Mentor Graphics UK | Subject: SpeedGate DSV
Edited by the Electronicstalk Editorial Team on 20 February 2002

FPGA prototyping speeds SoC verification

SpeedGate DSV (Direct System Verification) is an advanced verification environment for creating ASIC and SoC prototypes using off-the-shelf FPGAs

New from Mentor Graphics, SpeedGate DSV (Direct System Verification) is an advanced verification environment for creating ASIC and SoC prototypes using off-the-shelf FPGAs. Silicon prototypes created by SpeedGate DSV can be tested at speeds comparable to a real-time operating environment, significantly reducing costly, time-consuming silicon respins.

SpeedGate DSV adds a mid-priced ASIC verification technology to the industry's most complete verification flow that encompasses solutions from logic simulation to coverification.

Today, ASIC verification consumes 30 to 70% of total ASIC design time.

With costs for a 0.18-micron ASIC mask set exceeding $500,000, the financial impact of a silicon respin is substantial.

Persistent budgetary and time-to-market pressures require a solution that reduces the verification cycle, while maintaining a high level of accuracy.

SpeedGate DSV addresses all hardware prototype creation and verification challenges, from partitioning, debug and interconnect to rapid board creation and analysis.

By leveraging advances in commercially available FPGA technologies, SpeedGate DSV duplicates an ASIC design in an in-circuit environment.

SpeedGate DSV provides in-circuit verification in a moderately priced solution, running three to four orders of magnitude faster than low-end tools.

"SpeedGate DSV provides one of the most sophisticated and robust environments for partitioning and debugging ASIC and SoC prototypes", Rich Sevcik, senior vice president and general manager, Xilinx.

"Designers porting to our Virtex FPGAs using SpeedGate will find the most accurate representation of their designs in a cost-effective prototype".

"The versatility of SpeedGate DSV makes it a perfect complement to any existing verification flow", said Anne Sanquini, vice president and general manager of the HDL design Division of Mentor Graphics.

"For advanced flows making use of high-end emulation tools, SpeedGate DSV can be used to create low cost ASIC replicates that can be passed to software engineers for rapid system debug.

For cost-constrained methodologies, SpeedGate DSV delivers close to at-speed system verification at orders of magnitude faster than low-end solutions".

SpeedGate DSV is the most comprehensive and extensible solution for all aspects for the prototype design flow - partitioning, debug and interconnect.

It also links to board creation and analysis tools.

An interactive design cockpit launches partitioning and synthesis tools, and the completely scriptable interface plugs into any ASIC design environment - working hand-in-hand with emulation and gate-level simulation.

SpeedGate DSV includes a patent-pending advanced partitioning technology that enables designers to minimize the number of FPGAs used to prototype a design.

SpeedGate DSV fully supports the prototyping process with a team design environment, including sophisticated check-in/check-out features that track source code changes and manage version control.

SpeedGate DSV is available now at a price of $98,500 for a floating license.

SpeedGate DSV supports Sun Solaris 2.7 and 2.8 and supports ASIC partitioning on Xilinx Virtex FPGAs.

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