Product category: Intellectual Property Cores
News Release from: LSI Europe | Subject: Hydra
Edited by the Electronicstalk Editorial Team on 19 October 2004

Serdes core is flexible
about rates and standards

The Hydra serialiser/deserialiser (serdes) core offers a wide range of datarates, selectable I/O types, and exceptional design flexibility for fast SoC designs

The Hydra core is a preverified physical layer interface, supporting a large menu of industry-standard interfaces that significantly reduce the risk and turnaround time of product development for storage systems, networking, and telecommunications applications. The core can be easily integrated into a cell-based ASIC or into the RapidChip Xtreme family of slices.

"By leveraging our extensive experience in high speed serdes technology, we're providing a highly flexible and configurable core that satisfies the requirements of a broad cross section of custom logic applications", said Jean Bou Farhat, Vice President, CoreWare, LSI Logic.

"Both our ASIC and RapidChip Platform ASIC customers will benefit from having a single serdes that supports applications ranging from 155Mbit/s Sonet traffic to 3.125Gbit/s XAUI and CX4 interfaces".

Operating at 100Mbit/s to 3.2Gbit/s with in-system selectable LVDS and PCML I/O options, the Hydra core supports both 10bit parallel interfaces (10 or 20bit wide) and 8bit parallel interfaces (8 or 16bit wide).

In addition, for a given speed of operation, the core operates with a wide range of reference clock frequencies.

The core has full serdes capability including clock and data recovery circuitry on the receiver to recover both clock and data from a received bit stream.

Alternatively, the core may be configured to support source synchronous interfaces where a separate clock is sent with the data.

With this exceptional flexibility, the Hydra core supports a number of standards and dat rates including, but not limited to Gigabit Ethernet, SGMII, XAUI, CX-4, Serial RIO, Parallel RIO, SFI4.1, SPI4.2, SPI5, and HyperTransport.

The unique in-system selectable LVDS and PCML I/Os allow the design of single ports that support both LVDS-based and PCML-based interfaces such as SPI4.2 (LVDS) and XAUI (PCML).

System and custom logic designers using the RapidChip Xtreme family of slices with the Hydra core can now meet the most demanding high I/O bandwidth specifications with unprecedented levels of functionality at an affordable price.

"With today's myriad of interface standards, SoC designers are looking for ways to quickly and efficiently implement compliant interfaces so that they can concentrate their efforts on meeting unique systems requirements that differentiate their end products", said Jerry Worchel, principal analyst, In-Stat/MDR.

"By providing a single serdes core that supports a broad range of interfaces in a configurable manner for both ASIC and RapidChip Platform ASIC designs, LSI Logic is extending the flexibility of its RapidChip slices while also providing designers with the capability to support multiple standards with a single interface port".

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