ProcessorPM performs job of three different ICs

Lattice Semiconductor has introduced the ProcessorPM, a programmable, single-chip device for the reset generation, watchdog timer and voltage supervision functions.

The ProcessorPM integrates the functions of: reset generator ICs with variable pulse-stretch timing, watchdog timer ICs running up to two minutes and six-supply supervisor ICs.

Chris Fanning, vice-president of Lattice Semiconductor, said: 'The ProcessorPM device reduces our customers' costs by integrating functionality typically implemented using individual reset, supervisor and watchdog ICs.

'The ProcessorPM device also provides our customers with greater design flexibility by incorporating Lattice's in-system programmability.' The ProcessorPM device provides six programmable threshold comparators (accuracy of -0.7 per cent) with individual glitch filters to monitor up to six supply-rails without using external resistors or capacitors.

The comparator outputs are connected to a 16 macro-cell rugged on-chip PLD (programmable logic device) that generates the reset and brownout signals by using simple logic equations.

Four timers can be individually programmed from 32 microseconds to two seconds and used for implementing watchdog timers or for reset pulse stretching.

Two digital inputs can be used for manual reset inputs or for monitoring other digital inputs such as power-down or disable processor signals.

All device settings are stored using on-chip non-volatile EEPROM that is programmed via a JTAG interface.

Design modifications after the board is assembled, such as changing thresholds or altering timer values, can be achieved easily by modifying the design in PAC-Designer software and then downloading it into the design through JTAG.

There is no need to change resistors or capacitors.

ProcessorPM devices are pre-programmed with an initial configuration to integrate a programmable six-supply reset generator (configured through pin strapping) and a programmable watchdog timer (configured through pin strapping).

This configuration can be used across a large number of designs.

The original configuration software source-code enables integration of additional functions for further board-cost reduction.

ProcessorPM designs can be implemented using the intuitive, user-friendly GUI provided in version 5.1 of the PAC-Designer software tool suite, which can be downloaded for free from the Lattice website.

PAC-Designer 5.1 software's enhanced Logibuilder capability enables designers to reduce their solution cost.

The Logibuilder requires 20-30 per cent less PLD logic, enabling further integration of microprocessor support functions into the ProcessorPM device.

The ProcessorPM device can be customised for a given design environment in four simple steps.

The first step is to set up the monitoring thresholds.

Using a simple pull-down menu, the supply fault-detection thresholds for a given design can be set using 192 threshold steps for each of the voltage-monitoring inputs.

The second step is to configure the logic equation and timer-delay setting to meet the reset pulse stretching, output polarity and selected supply monitoring using the intuitive Logibuilder interface.

The third step is to iterate through the design using the waveform simulator.

The final step is hardware verification: downloading the design into a Processor Power Manager evaluation board and verifying the design in hardware before using it in schematic.

Samples of the ProcessorPM (24-pin QFNS package) device are now available.

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