Product category: Design and Development Software
News Release from: InnoLogic Systems | Subject: ESP-CV
Edited by the Electronicstalk Editorial Team on 10 March 2003

Verification tools boost
embedded memory yields

Virage Logic is using ESP-CV as part of its quality assurance programme to further increase the quality of its ASAP Memory product line

Virage Logic is using InnoLogic's ESP-CV product as part of its quality assurance programme to further increase the quality of its ASAP (area, speed and power) Memory product line. ESP-CV verifies 100% functional equivalence of its behavioural models and switch-level netlists. Dian Yang, President and CEO of InnoLogic, noted, "As the leading supplier of best-in-class semiconductor IP platforms, we are very pleased to have Virage Logic using our ESP-CV product.

Virage Logic's use of InnoLogic's products is an important validation of our unique verification solutions for custom silicon implementations.

Virage Logic's products are found in many of today's high performance SoC designs and ESP-CV's complete functional verification coverage contributes to Virage Logic's overall confidence in the quality of their products".

Raymond Leung, Vice President of Engineering and Operations for Virage Logic stated, "As we migrate our flagship ASAP Memory product line to 90nm process technology and below, it is absolutely critical that we maintain and further improve the quality of these products".

Leung continued, "ESP-CV integrated easily into our verification methodology and provided us with 100% functional coverage by directly comparing our behavioral model with switch-level netlist.

With InnoLogic's ESP-CV as part of our overall quality assurance program, we're confident that we're delivering the highest quality products to our customers".

Prior to using ESP-CV, Virage Logic was performing multiple simulation runs to verify the functionality of their memories.

However, the level of verification coverage using this method is dependent on the designer's ability to think of all possible conditions and the amount of time available to simulate those conditions.

Compounding this was the challenge of verifying many memory instances generated by the compiler.

With ESP-CV, Virage Logic is able to verify 100% of the design's functional space, covering all generated memory instances, without requiring designers to think of all possible conditions.

Virage Logic is using ESP-CV to verify its ASAP Memory product line and will be extending its use to verify other embedded memories such as the STAR Memory System and the NetCAM product line.

Leung continued, "By integrating ESP-CV into our overall methodology and design flow, we are able to further improve the verification coverage of our memories, while increasing productivity and time to working silicon".

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