Product category: Analogue and Mixed Signal ICs
News Release from: Inphi Corp | Subject: 1385DX
Edited by the Electronicstalk Editorial Team on 10 January 2008
Demultiplexer runs up to 12.5Gbit/s
Can be used to sample high-bandwidth analogue signals and demultiplex them to a lower datarate for postprocessing via a low speed FPGA or ASIC.
New from Inphi Corp, the 1385DX is a 1:8 demultiplexer with latched comparator input operating at bitrates from DC to 12.5Gbit/s Part of the High Speed Logic family of devices, the 1385DX, with its high sensitivity latched comparator input and autosynchronising demultiplexer, enables test and measurement, defence and aerospace designers to develop high-speed data-acquisition front ends and to deserialise high-speed signals
This article was originally published on Electronicstalk on 13 Oct 2004 at 8.00am (UK)
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"Validation of multigigabit serial interfaces in the next generation server memory architecture is difficult with extremely stringent performance and signal integrity requirements", says Levi Murray, Vice President, Technology Enabling and Infrastructure Development for Advanced Micro Devices.
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The 1385DX features a high-speed sampling clock and high-bandwidth latched comparator input that can be used to sample high-bandwidth analogue signals and demultiplex them to a lower datarate for postprocessing via a low speed FPGA or ASIC.
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Additionally, the high bandwidth input supports digital signals up to 12.5Gbit/s, which are latched and deserialised to an 8bit parallel output bus.
The 1:8 deserialisation, coupled with an on-chip synchronisation circuit and adjustable output levels, allow the use of multiple demultiplexers in parallel, with automatic alignment of the parallel output buses of the demultiplexers.
The 1385DX accepts a single external clock at up to 12.5GHz that samples the input signal from the high-bandwidth comparator.
Internally generated clocks are used for demultiplexing the latched input signal to an eightbit parallel databus.
The device outputs a full-rate clock (one-eighth of the input clock) or half-rate clock (one-sixteenth of the input clock) as determined by the clock-select input.
The demux's built-in synchronisation circuit allows two or more 1385DXs to be automatically synchronised using a master/slave mode, in which the slave demux synchronises to a signal (CK16) from the master, or a slave/slave mode, in which both 1385DX's are synchronised to an external master clock (one-sixteenth of the input clock frequency).
Synchronisation occurs within at most 152 periods of the input clock.
The 12.5Gbit/s 1:8 demultiplexer with latched comparator input operates from a standard +3.3V power supply.
It is currently shipping in preproduction quantities in an 8 x 8mm QFN package or on an evaluation board with SMA connectors.
Full production is expected to begin in Q1 2008.
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