RISC-based system controllers find distribution: News from GD Technik

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GD Technik is to distribute ESS Technology's new system controller chips designed for NEC's VR Series RISC microprocessors. This follows the signing of a joint technology and marketing agreement by ESS Technology and NEC under the terms of which ESS will develop enhanced versions of NEC's system controller chips used in digital consumer devices such as set-top boxes. Keith Jackson, GD Technik's technical director, explains: "Through ESS we are able to offer a portfolio of products for the expanding consumer electronics market.

In addition to supplying the company's state-of -the-art components, the launch of this new family of system controllers for NEC's microprocessors, is set to strengthen our position in the market for digital consumer electronic devices, where NEC's RISC processors have a leading market share".

The new ESS designed system controller chips offer a wide range of software and hardware features.

When combined with a VR Series microprocessor, the new system controller chips provide all the necessary features and performance required by the latest smart digital consumer devices, including set-top boxes and Internet appliances.

The controller integrates peripheral functions such as a memory controller, DMA controller, PCI bus host bridge and local bus host bridge.

ESS's systems controller range is expected to be available in the second half of 2002.

NEC's VR Series RISC microprocessors provide a comprehensive solution for embedded system designers.

Developed around the MIPS RISC architecture, all members of the VR Series are backward-code compatible and highly scalable.

NEC and ESS Technology provide efficient and flexible design tools to reduce development risks and time to market, for example development system and evaluation boards containing NEC microprocessors and ESS system controllers.

These systems are designed as platforms to develop and test peripheral hardware, device drivers and software applications as well as an evaluation board reference design.

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