Product category: Microprocessors, Microcontrollers and DSPs
News Release from: Fujitsu Microelectronics Europe | Subject: Leo FR-V
Edited by the Electronicstalk Editorial Team on 16 February 2001
Leo aims at
European navigation applications
Fujitsu Microelectronics Europe is releasing its Leo FR-V (Fujitsu RISC-VLIW) chip, based on the FR-V architecture announced last year
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The Leo chip is designed around Fujitsu's FR500 core and dedicated purely to the European navigation marketplace. Co-ordinated by Fujitsu Microelectronics in Frankfurt (FME), the design of the chip is being carried out by Fujitsu Microelectronics in Israel (FMIS), where the well-known SparcLite was produced.
Built using the powerful FR500, 32bit, four-way VLIW core with media and graphics enhancements, Leo is 100% software compatible with Fujitsu's MB93501 and is both modular and expandable, with the memory management unit being ARM compatible with Windows CE support.
The device operates at a low cost to the system, with an internal frequency of 266MHz, and features an external flexible and simple 32bit system bus operating at 66MHz, 1.8V, and a set of generic and automotive specific peripherals.
Fujitsu's FR-V architecture is exceptional as it is able to execute parallel instructions.
Further reading
Two 8bit microcontrollers for household appliances
A pair of 8bit microcontrollers have low power consumption and high performance making them suitable for use in household appliances and digital audio/video equipment
RISC-based MCU for automotive applications
The MB91F467B is designed in co-operation with major automotive customers and includes powerful peripheral functions and features to support a wide range of automotive and industrial applications
The compiler rather than the processor is responsible for guaranteeing simultaneous issuing of each packet.
Leo features six execution units on its processor: two integer units; two floating point units and two media execution units, all running in parallel, and its compiler decides which unit is going to carry out a command using the VLIW (very long instruction word) concept.
The CPU core provides a peak performance of 1064MIPS, 1.064GFLOPS or 4256MOPS at 266MHz (integer operation, floating-point and media), providing the possibility for more functionality and/or lower frequency operation.
Integrated within the design is an advanced SDRAM controller with a maximum bandwidth of 1Gbyte/s.
This is over an extended temperature range of -40 to 85C.
The chip design includes two caches - a four-way, dual ported 16Kbyte instruction cache, and a four-way, dual ported 16Kbyte data cache which is nonblocking, and has write back or write through functions.
A wide variety of peripheral functions are also featured and include: four UARTs; two CAN bus; SIO; I2C; 18 general-purpose IOs; three timers; a watchdog; two PWMs; three interval timers; eight interrupts; a real-time clock and a graphics display controller, supported by direct connection to Fujitsu's Cremson.
In addition to these an interface to a MOST transceiver of 25Mbyte/s is also included which allows the possibility of connecting multimedia over an optical bus.
Designed using 0.18 micron technology, the chip operates from a supply voltage of 1.8V internal/3.3V external, and has a power consumption of 2.5W at 266MHz.
Power management features of slow and stop mode can be used to lower the current.
The device is housed in a 320-pin FBGA, and JTAG and boundary scan test is applied to all I/O pins except for the SDRAM.
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