Product category: Intellectual Property Cores
News Release from: Denali Software
Edited by the Electronicstalk Editorial Team on 18 January 2007
DDR PHY spec makes awards shortlist
The recently announced DDR PHY Interface (DFI) specification has been selected among the finalists for the coveted DesignVision Award in the Interconnect Technologies and Components category
The winners of this prestigious award will be announced at DesignCon on Tuesday 30th January 2007 at noon in the theatre of the Santa Clara Convention Centre, San Jose, California. The specification is the result of a collaborative effort by industry leaders, ARM, Denali, Rambus, Intel, Samsung and Synopsys to describe a common interface between DDR-DRAM memory controller logic designs and DDR DRAM physical interface (DDR PHY) designs.
This article was originally published on Electronicstalk on 18 January 2007 at 8.00am (UK)
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'Our DesignVision Awards honour those catalysing positive change in high-technology, business, and academia, completely in line with the IEC's mission', states John Janowiak, President of the International Engineering Consortium.
'We are delighted to recognise our DesignVision finalists and share the best design advancements and innovators with the entire industry'.
The DFI specification defines a common interface between the memory controller logic and the PHY interface to reduce cost, time to market, and increase the potential for reuse of the individual components that make up the memory system.
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'Intel recognised the importance of a common interface with the DDR controller and Physical interface allowing better and faster reuse for third party intellectual property suppliers in this space', said Bryan Jones, External Intellectual Property Programme Manager, Ultra Mobility Group at Intel Corp.
'It's nice to see the industry recognising the importance of this specification'.
'I want to personally thank all the contributors for their participation'.
'The collaborative efforts of the DFI contributing members has resulted in a interconnect standard that is focused on simplifying complexity, reducing time to tapeout, while enabling a broader selection of complementary memory IP solutions', remarked Navraj Nandra, director of Mixed-Signal IP at Synopsys.
'We congratulate Denali and the other contributing members on this welcomed recognition'.
'We are excited to be nominated for this prestigious award', said Brian Gardner, Vice President of IP Products at Denali.
'This specification has been downloaded by over 700 various users since its announcement on September 13 at the widely attended MemCon event'.
'This momentum behind this specification, as result of various companies, has truly been a critical asset and benefited customers implementing high performance memory interface solutions'.
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