Product category: Intellectual Property Cores
News Release from: Denali Software | Subject: DDR2 SDRAM PHY
Edited by the Electronicstalk Editorial Team on 24 September 2007
Memory PHY reduces LSI design risks
DDR2 SDRAM PHY design can be prototyped on the Xilinx Virtex-5 FPGA before progressing to Tokyo Electron Device ASICs.
Tokyo Electron Device and Denali Software have collaborated to develop and release a DDR2 SDRAM PHY design that runs on the Xilinx Virtex-5, the largest and fastest FPGA in the world The PHY is fully compatible with DDR PHY Interface (DFI), which is the industry-standard interface for DDR memory controller and PHY
This article was originally published on Electronicstalk on 5 Aug 2005 at 8.00am (UK)
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