Product category: Electronics Manufacturing Machinery and Materials
News Release from: DEK | Subject: Backside wafer coating process
Edited by the Electronicstalk Editorial Team on 23 June 2005
Backside wafer coating process on show
DEK will show off its unique, cost saving and throughput enhancing packaging technologies at this year's Semicon West event in San Francisco, California
Through detailed process research and analysis combined with some unique enabling technologies, DEK has successfully created and implemented some extremely innovative solutions for today's semiconductor packaging manufacturers and will display many of these solutions at the upcoming show. Among the highlights of the DEK exhibit will be a demonstration of the company's backside wafer coating process, which allows high throughput on a cost-effective mass imaging system and is capable of exceeding the +/-12.5um total thickness variation (TTV) required by most wafer processing manufacturers.
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Imaging platform turns to backside wafer coating
Long recognized as the world leader in high accuracy mass imaging technology, DEK has led the way with yet another cost-effective packaging solution
Mass imaging platform runs backside wafer coating
A new high throughput backside wafer coating process is capable of exceeding the +/-12.5mm total thickness variation stipulated by most wafer processing specialists
Enabled by DEK's metal stencil and emulsion screen technologies, materials can be deposited accurately at high speed, while achieving ultimate control over print thickness and ensuring uniformity at high production volumes.
This process will be shown on DEK's leading-edge, Micron-class Galaxy printer platform, the ultimate system for high-accuracy packaging applications.
DEK has pioneered several unique packaging processes that address today's requirements of precision, reliability and extremely high throughput - all at a reduced cost per package.
Further reading
Mounting process makes stencils easier to use
Novel stencil system extends VectorGuard range to deliver enhanced manufacturing flexibility
Some of these applications include thermal interface material (TIM) imaging and wafer bumping solutions enabled by DEK's patented ProFlow Direkt imaging technology, encapsulation that only requires one print stroke, singulation technology using virtual panel tooling (VPT), repeatable ball placement technology and high speed substrate bumping.
DEK will be on the the Alphasem booth (7111) at Semicon West 2005, from 12th to 14th July 2005 at San Francisco's Moscone Centre.
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