Product category: Design and Development Software
News Release from: DeFacTo Technologies
Edited by the Electronicstalk Editorial Team on 07 March 2005
New name in design-for-test market
DeFacTo Technologies aims to leverage patent-pending DFT technology, develop products and services for the worldwide electronics market and become the leading provider of DFT tools.
A group of experts in the design for test (DFT) of electronic systems have launched DeFacTo Technologies to leverage patent-pending DFT technology, develop products and services for the worldwide electronics market, and become the leading provider of DFT tools For the past two years, the company has been working with one of the largest semiconductor manufacturers in Europe to validate the benefits of its tools
This article was originally published on Electronicstalk on 7 May 2004 at 8.00am (UK)
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DeFacTo was founded in 2003 and raised Series A financing late last year.
The development of DeFacTo's technology was begun at the National Polytechnic Institute of Grenoble (INPG-France) in 1997, under the leadership of Chouki Aktouf, PhD.
More than 18 man-years of work were applied to this unique approach to DFT.
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The DeFacTo executive team includes: Dr Aktouf, President and CTO; Michel Oger, Vice President of Business Development; Philippe Duchene, Vice President of Engineering; and James Girand, President of US Operations.
"The semiconductor industry is reaching a breaking point", said Dr Aktouf.
"Traditional DFT solutions are confined to the structural level; they come late in the design process, and therefore are disconnected from main design decisions".
"This results in unpredictable development times and high development costs - as much as 10 to 25% of total design cost".
"In addition, the lack of DFT-ready semiconductor intellectual property (IP) is hurting the industry's ability to develop chips quickly".
"The design reusability effort does not include design for test issues".
According to the International Technology Roadmap for Semiconductors, testing may account for more than 70% of a chip's total manufacturing cost.
There is consensus that the increasing complexity of designs is increasing costs and stretching the limits of existing design tools, and that moving DFT to a higher level of abstraction helps address these challenges.
Indeed, the most cost-effective approach - in terms of engineering resources and time-to-market - is to start performing accurate design analysis as early as possible in the design cycle.
The chip design flow has three major levels of abstraction: register transfer level (RTL), gates and layout.
DFT insertion is a design step on which other design steps depend.
Until now, DFT solutions have been stuck at the post-synthesis gate level.
"If it is to continue to reduce development cycle time and costs, the industry has no other choice but to move DFT to a higher level of abstraction - that is, before the synthesis process ever takes place", added Dr Aktouf.
"So far, the main obstacle to doing this has been the inability to guarantee DFT quality and 'synthesisability' - without synthesising".
When ready for market, DeFacTo's tools are expected to become the de facto standard for DFT.
The tools include solutions for scan and built-in self-test (BIST) at the register transfer level.
DeFacTo's tools will fit nonintrusively into existing integrated circuit design flows, and will be used in parallel with other tools such as automatic test pattern generation and additional complementary DFT solutions.
The tools will accept the same synthesisable RTL designs as those accepted by Synopsys' Design-Compiler and other industry-standard logic synthesis tools.
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