News Release from: CoWare
Edited by the Electronicstalk Editorial Team on 7 March 2002
Interface synthesis removes bus guesswork
CoWare has enhanced its CoWare N2C design system with second-generation interface synthesis capabilities, enabling designers to develop optimal architectures for the latest complex SoC designs.
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CoWare has enhanced its CoWare N2C design system with second-generation interface synthesis capabilities, enabling designers to develop optimal architectures for the latest complex SoC designs. These capabilities solve one of the most difficult problems in today's designs - finding the bus architecture that gives the best tradeoff of high performance and low power. This design decision has a huge impact on the end product, but the latest generation of SoC buses allow so many possibilities that designers can only take their best guess at the optimal architecture.
CoWare N2C removes the guesswork in making these tradeoffs and implementing the designs.
This capability has been proven in production designs using the amba 2.0 on-chip interconnect and STMicroelectronic's STBus.
"Many of our new SoC designs use the advanced features available in the STBus", stated Jean-Marc Chateau, Director of Design, Consumer and microcontroller Groups, STMicroelectronics.
"We worked with CoWare to enhance CoWare N2C to easily build platform variants exploiting these advanced features.
We've found that different architectures can make a tremendous difference in power and performance in the end products - up to a 50% difference in performance in one case".
In addition, CoWare worked closely with ARM to develop this new technology for STMicroelectronics and other ARM Partners.
"As more designers take advantage of the flexibility and ease of implementation that AMBA technology offers, they need - to be able to explore the wide range of design possibilities open to them", stated Jonathan Morris, ARM's System Infrastructure Program Manager.
"Now, with CoWare N2C, our mutual customers can efficiently test different AMBA technology-based architectures to find the optimal trade-off of performance and power for their latest portable consumer devices".
Today's leading interconnect solutions allow many architectural alternatives to be explored, but this carries a significant simulation overhead for the manual RTL designer.
CoWare's unique design system provides the tools and methodology to model, synthesise and evaluate different bus architectures quickly.
SoC designers are now finding that complex interconnect architectures must be simulated and analysed with sufficient accuracy before committing to an implementation.
CoWare N2C allows designers to build an accurate simulation model for different config-urations very quickly.
The architect specifies graphically which bus masters connect to which bus slaves via which node.
Each node produces a distinct bus or bus layer.
CoWare's new second-generation interface synthesis technology, configured by this high-level input, automatically synthesises the bus interconnect matrixes and crossbar switches, which are at the heart of these multilayer buses.
The necessary arbitration logic for multiple bus masters, along with all other bus logic, is also synthesised.
Following simulation, CoWare N2C's powerful analysis tools let designers check the performance of different configurations.
To change from one bus configuration to another, the designer simply adjusts the high-level input and resynthesises.
Once the optimal bus architecture is established, the hardware design can be validated and implemented in an RTL-based design flow.
This significantly speeds the hardware design process.
CoWare's second-generation interface synthesis technology has already been deployed in production designs and is now in limited release to a select group of leading systems and semiconductor houses for designs using AMBA on-chip interconnect or STBus.
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