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Product category: Design and Development Software
News Release from: Carbon Design Systems | Subject: SOC-VSP
Edited by the Electronicstalk Editorial Team on 7 December 2005

SoC tool suite
becomes design language agnostic

SOC-VSP complements the power of ARM RealView SoC Designer by importing Verilog and/or VHDL (RTL) into a RealView SoC development environment

Carbon Design Systems has rolled out its breakthrough SOC-VSP product line that complements the power of ARM RealView SoC Designer solution by importing Verilog and/or VHDL (RTL) into a RealView SoC development environment. This combination allows a hardware-accurate SoC model with RTL to be profiled, optimised, debugged and validated including the software and hardware content.

System architects, software developers, and hardware designers can validate design assumptions and implementation throughout the design cycle.

System architects can profile a SoC with cycle-count accuracy and certified models to find software bottlenecks and discover optimal hardware configurations.

Software developers can get an early jump on debugging their firmware on a hardware-accurate mode - rather than waiting months for silicon or a behavioural model to be developed.

Hardware designers can leverage fast mixed-level simulation, an integrated debugger, and a plug-and-play interface to an amba AHB interconnect, Amba APB interconnect, or Amba 3 AXI interconnect.

This is the first all-software, all-inclusive product of its kind to enable continuous validation of software and hardware from concept to volume production.

'This end-to-end integration will enable our customers to use the RealView SoC Designer with both existing and newly developed RTL early in the design cycle to make informed design tradeoffs and carry out inclusive software and hardware validation', explained Chris Lennard, ESL Technical Marketing Manager, ARM.

'Transparent support of both Verilog and VHDL hardware descriptions, like the support provided by Carbon's SOC-VSP solution, is critical for today's complex SoC designs that have IP incorporated from multiple sources'.

'The ESL adoption barrier has finally been broken with the advent of SOC-VSP', said Steve Butler, President and CEO of Carbon Design Systems.

'Waiting for behavioural models of the RTL to be developed is a thing of the past'.

'This SoC development tool suite is design language agnostic and lets users easily mix and match C, SystemC, Verilog and VHDL'.

Compiled RTL can now become an integral part of the RealView SoC Designer's system partitioning, profiling, debugging and simulation.

SOC-VSP's component wizard enables Verilog and/or VHDL to be easily incorporated into the design environment of the RealView SoC Designer.

Bus protocols are selected; clock, interrupt, and reset signals are defined; RTL is compiled; and a component is automatically added to the ARM RealView Model Library.

These model components can be easily 'dragged and dropped' onto its design canvas along with processors and peripheral models.

Components are easily connected to an Amba interconnect by simply drawing lines and assigning bus attributes.

Once the architecture is defined, embedded software can be executed on the underlying hardware and both the software and the hardware can be profiled together.

All standard debugging features are supported - single-stepping of source code; setting breakpoints; tracing registers, memories and signals - with 'Carbonised' RTL hardware models.

RealView SoC Designer's waveform viewer is transaction-aware and animates both transactions and signals.

Now, Verilog and VHDL models can be interrogated as standard components.

SOC-VSP supports 100% visibility for all RTL signals, registers and memories.

Carbon and ARM have created an industry first by providing save and restore for a complete SoC modelling environment that includes Verilog and VHDL.

Firmware and the underlying hardware can be validated and check-pointed at any time.

Typically, once a bug is discovered and fixed, perhaps days into a simulation, the simulation would need to be repeated to verify the 'fix'.

With SOC-VSP, the simulation state can be saved and restored, to jump days into the simulation and validate the bug fix.

This feature not only allows quick verification of bug fixes, but enables much longer simulations by not rerunning previously validated code.

With the growth in software content in SoC design and overall hardware complexity, save and restore is a requirement for a robust SoC development environment.

Carbon's SOC-VSP software product will begin shipping on 30th December 2005 with per seat pricing based on an annual subscription volume model.

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