Product category: Intellectual Property Cores
News Release from: Cambridge Consultants | Subject: APE2
Edited by the Electronicstalk Editorial Team on 11 February 2003
DSP core uses adaptive datapath to speed
to 1BOPS
A novel DSP core is claimed to establish a new price/performance benchmark for low-end SoC/ASIC applications.
Cambridge Consultants (CCL) has launched an innovative DSP core it reckons establishes a new price/performance benchmark for low-end SoC/ASIC applications Despite the core's very compact design - facilitating a 16bit implementation using as few as 7000 gates for example - a novel adaptive datapath architecture delivers startling computational throughput
This article was originally published on Electronicstalk on 7 Sep 2004 at 8.00am (UK)
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Advanced application-specific performance is achieved by allowing users to configure and customise the core's VLIW (very long instruction word) processing architecture, together with a highly parallel structure featuring dynamic datapath routing.
Processors may easily be configured to perform 10 parallel operations per cycle for instance, delivering 1BOPS throughput at a 100MHz clock rate - in a silicon area that equates to a volume manufacturing cost of a few cents Dubbed APE2, the new DSP core forms part of CCL's commercial silicon intellectual property library, CCLasic, and has already been field-proven on SoCs for software-defined radio as part of the consultancy's product design work.
"Most commercial DSP IP is targeted at high end applications and is difficult to cost-justify for cost-sensitive volume products, forci