Product category: Design and Development Software
News Release from: Cadence Design Systems
Edited by the Electronicstalk Editorial Team on 14 May 2007
Expanded alliance assists IC verification
Certified partners extend verification resources and expertise for design teams facing verification-resource limitations
Cadence Design Systems has certified 22 new Incisive Plan-to-Closure Methodology Verification Alliance Partners. The Plan-to-Closure Methodology-certified partners extend verification resources and expertise for design teams facing verification-resource limitations. Partners are trained and qualified in 'high-demand' areas such as SystemVerilog, transaction-level verification, assertion and coverage-driven verification, and system-level verification.
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In order to be certified, new members are required to attend Plan-to-Closure Methodology-based training and encouraged to get focused training in one of the four areas including: planning and management, assertions and formal, universal verification reuse, or full-system-level verification.
Once members attend the course, they are signed off by a technical sponsor and gain Plan-to-Closure-Methodology certification.
'Yogitech has been delivering quality verification IP for some time and we trust the Plan-to-Closure Methodology to address IP-integration challenges by helping us deliver high-quality verification IP', said Silvano Motto, CEO, Yogitech.
'As an initial Plan-to-Closure-qualified member we look forward to continued improvement in our development process as we develop universal verification components in SystemVerilog and e'.
'There's now broad acceptance that one of the keys to addressing verification complexity is a well engineered and executed methodology', said Rob Hurley, CEO, Doulos.
Further reading
Software takes holistic view of PCB design
System interconnect design platform adds new capabilities at all stages of printed-circuit board design
Single simulator covers all IC technologies
End-to-end simulation and verification software for custom IC uses a common database of netlists and models to simulate analogue, RF, memory and mixed-signal designs
Kit cuts the cost of low-power IC design
Design kit enables engineers of different experience levels to adopt advanced low-power techniques with minimal risk and deployment effort
'High-capability training that addresses both methodology and language is vital to effective execution'.
'Our commitment to this program will enable customers implementing Plan-to-Closure-based environments get best-fit training'.
Members are also encouraged to spend scheduled time contributing and participating in the Plan-to-Closure-Methodology Web community by sharing examples and experiences around verification-IP development and protocol expertise.
This Web- based knowledge system allows for partners and users to seek advice, share ideas, and gain access to additional methodology resources to help automate IP adoption and facilitate reuse within system-level project development.
'XtremeEDA's broad experience implementing verification-methodology programs for leading customers made us qualified Plan-to-Closure-Methodology partners', said Claude Cloutier, CEO, XtremeEDA.
'We found the approach to be extremely thorough with the ability to add much higher levels of predictability and scalability to plan, measure and react accordingly at the project level'.
'Many organisations realise that they are up against serious verification-resource limitations, and need proven step-by-step options for designers', said Steve Glaser, Corporate Vice President, Marketing, Verification Division at Cadence.
'These newly certified partners will add to the Plan-to-Closure-Methodology community, and make adoption and deployment of best practices simpler and much more readily available for our worldwide customers'.
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