Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter L, XL and GXL
Edited by the Electronicstalk Editorial Team on 15 September 2005
Digital design platform
comes in three levels
The Cadence Encounter digital IC design platform now offers a tiered range of products scaled to different complexities of digital IC design
Cadence Design Systems has developed a new product segmentation strategy to provide customers with multiple levels of technology tailored to specific levels of design complexity. In support of this new strategy, the Cadence Encounter digital IC design platform now offers a tiered range of products scaled to different complexities of digital IC design, including its new Masterplan automatic floorplanning technology.
Related stories
Design platform enable DDR integration at 65nm
Cadence Design Systems and Denali Software have delivered an advanced DDR-PHY implementation methodology based on the Cadence Encounter digital IC design platform
Methodology combines design with verification
Fujitsu Kyushu Network Technologies is using the Cadence Incisive plan-to-closure methodology for SystemVerilog verification in RTL logic design teams
The new Encounter offerings are tiered into three levels, Encounter L, XL and GXL.
The Encounter L product series provides an easy-to-use, integrated, value-priced implementation environment for less complex, flat designs at 150nm and above with gate counts below 5 million gates.
The Encounter XL product series targets large-scale, high-performance, hierarchical designs over 5 million gates at 130, 90 and 65nm, and features Masterplan automatic macro placement and floorplanning technology.
A third series, Encounter GXL, is scheduled for delivery in the fourth quarter of 2005.
The Masterplan feature within the Encounter XL series reduces the design effort required to design the physical architecture for very complex SoC designs.
Further reading
Software takes holistic view of PCB design
System interconnect design platform adds new capabilities at all stages of printed-circuit board design
Single simulator covers all IC technologies
End-to-end simulation and verification software for custom IC uses a common database of netlists and models to simulate analogue, RF, memory and mixed-signal designs
Kit cuts the cost of low-power IC design
Design kit enables engineers of different experience levels to adopt advanced low-power techniques with minimal risk and deployment effort
This includes high-end networking, graphics and processor ICs with hundreds of embedded memories and hard IP blocks which are typically placed manually.
Unlike conventional automation approaches that focus strictly on projected wire length, the Masterplan feature within the Encounter XL series works by optimising overall chip signal flows.
The result is an expert-quality chip plan in a fraction of the time typically taken.
'We have successfully started to use Masterplan automatic floorplanning in our production designs', said Hisaharu Miwa, Deputy General Manager, Design Technology Division, LSI Product Technology Unit at Renesas Technology Corp.
'It allows us to create an automatic floorplan for multi-million-gate designs with hundreds or even thousands of hard macros in minutes or hours, as opposed to the days or weeks it formerly took'.
'Masterplan is key to our goal of reducing overall design cycle time on high-complexity nanometre designs'.
'Many complex designs consist of hundreds of hard macros'.
'Automatically creating a floorplan for such designs is a difficult problem', said Nobuyuki Nishiguchi, Vice President and General Manager, Development Department 1 of STARC.
'We have been evaluating Masterplan from the beginning, and we have found that it automatically produces much better initial floorplan results than other existing tools available in the market'.
'Starting with the Masterplan results, our designers will dramatically shorten turnaround time to reach the final floorplan'.
'We are looking forward to current and future enhancements of automatic floorplanning features for our production deployment'.
'We are excited to bring the latest IC Implementation technology to our customers', said Wei-Jin Dai, Corporate Vice President, R and D for Cadence.
'With Masterplan automatic floorplanning, the Encounter platform further extends its lead in high-end digital IC design, while the Encounter L series serves the needs of mainstream designers'.
The First Encounter L and First Encounter XL silicon virtual prototyping products, and SoC Encounter L and SoC Encounter XL full implementation products, will be available in September 2005.
• Cadence Design Systems: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Related Business News
Icoa Is Partnering With Anchorfree To...
...Enhance And Monetize Thousands Of Wi-fi Hotspots. Icoa, Inc., a national provider of wireless broadband Internet access and managed network services in high-traffic public locations, and AnchorFree Inc., a rapidly growing Wi-Fi community powered by advertising, have announced today that they are partne
Eds Sales Take A Tumble
Dave Friedlos, Computing , Thursday 17 May 2007 at 00:00:00 But experts say downturn may reflect market weakness, writes Dave Friedlos Outsourcing giant EDS has released disappointing first-quarter figures showing slower growth and fewer con
Sweet specialist sees growth spurt
Lara Williams, Computing , Thursday 17 May 2007 at 00:00:00 Confectionary company IT infrastructure overhaul accommodates rapid growth Confectionery supplier Bon Bon Buddies has overhauled its IT infrastructure to cope with rapid growth whic
Canon takes a better picture of its supply chain
Lara Williams , Computing , Thursday 17 May 2007 at 00:00:00 Imaging specialist improves sales forcasting by 20 per cent Imaging specialist Canon has improved the accuracy of product sales forecasting by more than 20 per cent using supply ch
Search the Pro-Talk network of sites
