Product category: Design and Development Hardware
News Release from: Cadence Design Systems | Subject: Physical Verification System
Edited by the Electronicstalk Editorial Team on 15 September 2005
Verification system optimised for rapid turnaround
The Cadence Physical Verification System is optimised for rapid turnaround of design rule check and layout versus schematic.
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The Cadence Physical Verification System is optimised for rapid turnaround of design rule check (DRC) and layout versus schematic (LVS). The system's massively parallel approach facilitates multiple design turns per working day - even for the largest designs at 90nm, 65nm and below that would otherwise require overnight or multi-day runs. The Cadence Physical Verification System uses an innovative approach to design data processing that combines proven accuracy, high performance, dedicated processing engines, concurrent reporting of results and a massively parallel architecture.
This combination of new capabilities delivers near-linear performance scaling across very large numbers of CPUs and compared with conventional tools, significantly reduces physical verification cycle time as well as the overall number of cycles required.
With these capabilities, designers can improve schedule predictability, free time to focus on yield optimisation, and simplify the management of rule complexity challenges arising from subwavelength lithography and manufacturing effects.
'The Cadence Physical Verification System is the leading solution that addresses Fujitsu's needs for advanced sub-90-nanometre designs and that also delivers the performance scalability we require to reach 65 nanometres and below', said Shoji Ichino, General Manager, LSI Technology Development at Fujitsu.
'The system offers outstanding performance, concurrent results reporting, and superior integration with the Virtuoso platform and OpenAccess'.
'The Cadence Physical Verification System is in production use by our worldwide design teams for 90- and 65-nanometre physical verification and its extensibility will be used in the future to address manufacturing and yield optimisation'.
The Cadence Physical Verification System employs a multiple-strategy partitioning approach that removes the throughput limitations of conventional physical verification solutions and which leverages the full power of cost-effective, distributed processing platforms.
The dedicated processing engines simplify rule deck authoring and maintenance, enhance quality of results and take full advantage of the system's highly scalable, distributed processing environment to further improve performance.
The new system features several industry-first capabilities that accelerate chip time to market.
A concurrent debug capability ensures the most productive use of physical verification runtime.
It delivers debug results during runtime, via OpenAccess 2.2, directly into an integrated Virtuoso-based environment.
Designers can start to debug designs immediately after launching a physical verification run and fix errors in parallel with job execution.
This allows them to quickly identify problems and eliminate wasted time by terminating the run if they discover serious design flaws.
Dr Marc Levitt, Vice President, Design for Manufacturing, at Cadence, said: 'The Cadence Physical Verification System allows design teams to process leading-edge designs over lunch that require overnight or days-long runs with conventional tools'.
'The new system exceeds the current throughput demands of the largest designs from our leading-edge customers, and delivers the performance scalability required to meet their future demands down to 45 nanometres and beyond'.
The Cadence Physical Verification System is closely integrated with industry-standard design solutions from Cadence, including the Virtuoso and Encounter platforms, as well as Cadence parasitic extraction products and resolution enhancement technologies (RET).
In alignment with Cadence's newly announced product segmentation strategy, the Cadence Physical Verification System is available in tiered configurations, starting with a single CPU desktop L configuration and an XL configuration featuring scalable, parallel processing with dedicated processing engines.
The product segmentation strategy provides customers multiple product configurations tailored to specific levels of design complexity.
The Cadence Physical Verification System also offers designers minimal startup time and an easy migration path from current solutions.
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