Laurence Marchini, Editor, writes:
We see from your search that you're looking for information on the term "Resolution enhancement", and we have a large number of manufacturers' news releases and technical articles here on Electronicstalk which will be of interest. Let me be your guide.
Start with the news release Measurement link aids optical proximity correction from Synopsys, which we summarised at the time by saying "Design for manufacturing interface helps customers to develop faster, more accurate and predictive OPC models for advanced 45nm and beyond technologies". Earlier in the week, we featured the news release Acquisition delivers powerful design-to-fab flow from Mentor Graphics UK: "Mentor Graphics Corp has acquired Sierra Design Automation for US $90 million in cash and stock".
In February 2007, we covered the news from GenISys - take a look at EVG and Genisys combine on lithography simulation which says: "EV Group (EVG) has formed a collaborative product development partnership with Genisys for the development and marketing of a simulation platform for advanced mask aligner lithography processes".
Take a look also at the news release from ASML, Imaging, overlay and throughput improvements, as well as Next-generation OPC solution from Mentor Graphics from Mentor Graphics UK, and Cell BE processor to accelerate EDA from Mercury Computer Systems.
See also:
Compression algorithm cuts mask files down to size (October 2006)
MEBESzip is a software product that compresses mask data files in MEBES format by a factor of 5-15x and significantly reduces file sizes as well as data transfer times
Design flow overcomes lithographic limitations (October 2006)
Cadence Design Systems has created a lithography-aware design flow and has defined an interface that will link resolution enhancement technologies with physical design and verification
Sematech seeks out next-generation lithography (September 2006)
Sematech has awarded a contract to qualify the imaging performance of advanced logic patterns, metrology structures and defect designs for the 45, 32 and 22nm technology nodes
Design rule checker adapts to the nanometre era (July 2006)
Calibre nmDRC redefines traditional design rule checking by dramatically reducing total cycle time and integrating critical elements such as critical area analysis and critical feature identification
TCAD tools run on dual-core processors (June 2006)
A new Sentaurus TCAD release add