Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter
Edited by the Electronicstalk Editorial Team on 02 August 2005
Platform accelerates structured ASIC to
silicon
This month, Fujitsu Microelectronics America will ship initial production volumes of a new, highly complex, structured ASIC using Cadence Encounter digital IC implementation.
This month, Fujitsu Microelectronics America (FMA) will ship initial production volumes of a new, highly complex, structured ASIC using Cadence Encounter digital IC implementation Encounter, which was originally developed for standard ASICs, provided rapid timing closure with signal integrity for optimal quality-of-silicon (QoS) in the implementation phase of the design flow for FMA's AccelArray family of structured ASICs
This article was originally published on Electronicstalk on 15 Apr 2004 at 8.00am (UK)
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Toshiba America Electronic Components (TAEC) has successfully implemented an 8-million-gate SoC using the Cadence Encounter digital IC platform.
Signal integrity tool spots damaging glitches
Cadence Design Systems has made significant enhancements to its CeltIC 4.1 signal integrity solution, a key technology of the Encounter digital IC design platform for nanometre-scale IC designs.
"We chose the Encounter platform as the netlist handoff and for completion of physical design such as the placement and routing, because it provided excellent flexibility in implementing standard ASIC and structured ASIC designs", said Noboru Yokota, Senior Director of Engineering at FMA.
"This very complicated design, which FMA completed with AccelArray Giga Frame, implements about 1.4 million instances of cell".
The design incorporates 3.5 million logic gates, 119 instances of 2RW SRAM (40 x 512), 33 instances of register file (40 x 32) and 12-channel, 3.125Gbit/s serdes for high-end servers developed for consumer applications.
Further reading
Encounter speeds Wintegra's nanometre designs
Wintegra has deployed the Cadence Encounter digital IC design platform to take the next step into the challenge of nanometre design technology.
RTL compiler synthesis speeds multicore design
Toshiba America Electronic Components has used the Cadence Encounter digital IC design platform with nanometre synthesis technology to deliver a 530MHz synthesisable 64bit dual-issue MIPS core.
The design was completed with low, nonrecurring costs by using AccelArray Giga Frame.
"We are very happy with the success of our work with important customers such as Fujitsu", said Wei-Jin Dai, Platform Vice President, Digital IC Implementation at Cadence.
"This is another example of the Cadence Encounter platform's rapid route to complex, high-performance SoC implementation".
The Fujitsu AccelArray Giga platform addresses the specific needs of mid-volume vertical markets that require the performance of cell-based ASICs.
These platforms leverage Fujitsu's decades of ASIC design and system-level expertise in the networking, storage networking, next-generation consumer electronics and imaging markets.
Giga platforms reduce back-end physical design time such as DFT insertion, power mesh, clock tree synthesis and simultaneous switching output (SSO) analysis, all of which can consume a considerable amount of time.
The Giga platform offers up to 75Gbit/s of full-duplex serdes aggregated bandwidth by incorporating prediffused universal G-PHY macro cells.
SoC Encounter GPS combines RTL synthesis, silicon virtual prototyping, and full-chip implementation into a single system.
It enables engineers to synthesise to a flat virtual prototype implementation-including full-chip, routed wires-right at the beginning of the design cycle.
With SoC Encounter GPS, engineers have an early, accurate view of whether the design will meet its targets and be physically realisable.
Designers can then choose either to complete the final implementation or to revisit the RTL design phase.
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