Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter
Edited by the Electronicstalk Editorial Team on 07 May 2003
RTL compiler synthesis speeds multicore
design
Toshiba America Electronic Components has used the Cadence Encounter digital IC design platform with nanometre synthesis technology to deliver a 530MHz synthesisable 64bit dual-issue MIPS core.
Toshiba America Electronic Components (TAEC) has successfully used the Cadence Encounter digital IC design platform with nanometre synthesis technology to deliver a record-breaking 530MHz (typical operating condition) synthesisable 64bit dual-issue MIPS core Cadence RTL compiler synthesis, recently acquired with the purchase of Get2Chip, and the NanoRoute Ultra signal integrity and timing-optimised router worked together seamlessly to produce this complex multi-million-gate 130nm seven-layer metal CPU design
This article was originally published on Electronicstalk on 15 Apr 2004 at 8.00am (UK)