Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Virtuoso RF IC flow
Edited by the Electronicstalk Editorial Team on 25 January 2005
Design flow addresses
to wireless challenges
New software aims to give wireless chip designers and manufacturers better insight into the mixed-signal and radio frequency challenges that significantly impact wireless design
Cadence Design Systems has developed new capabilities that give wireless chip designers and manufacturers better insight into the mixed-signal and radio frequency (RF) challenges that significantly impact wireless design. Built on the leading Virtuoso custom design platform, this Cadence wireless offering combines new Cadence RF extraction technology, two new design flows tailored for wireless chip design, engineering services, silicon-proven IP, and integration with technology from industry-leading Cadence partners Agilent, CoWare, Helic and MathWorks.
This article was originally published on Electronicstalk on 25 January 2005 at 8.00am (UK)
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This offering provides access to a streamlined design process resulting in fewer respins and faster time to market.
In December 2004 International Business Strategies reported that parasitics are the leading cause of failures in wireless designs.
These issues are directly addressed by the system/integrated circuit (IC) flow, and the RF IC flow featuring Assura RF, new Cadence technology that delivers complete extraction for RF design.
'The Virtuoso RF IC flow is a significant step forward and provides wireless designers with a substantial time-to-market advantage'.
'The fact that Cadence uses real-world designs to streamline RF IC design front-to-back increases confidence and ensures faster implementation and adoption of new technology', said Dr Werner Geppert, Director, analogue design Methodology, Infineon Technologies.
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'We look forward to continued collaboration with Cadence in this area'.
Based on 802.11b wireless LAN design IP, the two new design flows included in the new Cadence wireless offering focus on front-to-back RF and analogue/mixed signal design while at the same time bridging the gap between IC implementation and the entire system design.
These flows enable simultaneous verification of the RF, analogue and digital domains together and verification of the wireless IC design in the context of the system.
The flows integrate technology from Cadence partners to help streamline wireless design.
Designers using Cadence Virtuoso AMS Designer can work with system design teams while leveraging the proven set of wireless standards libraries available for CoWare's SPW product.
They also can move a design from the system level to the IC level more efficiently through the integration of MathWorks' Matlab/Simulink with Virtuoso AMS Designer.
Also included in the flows are Agilent's proven RF design and test technologies - RFDE, Momentum and Ptolemy - and Helic's VeloceRF, an advanced inductor design solution that minimises errors associated with RF IC design cycles.
Wireless designers who are looking for accelerated wireless flow ramp up can also benefit from Cadence wireless engineering services capabilities.
These capabilities range from automated PDK development and customised flow implementation to full chip design and supply chain management.
Silicon-proven IP is also available for specific wireless applications to shorten design cycle time.
'Cadence is looking forward to working even more closely with wireless designers and business leaders as we expand our focus on this market segment', said Felicia James, Vice President and General Manager of the Cadence Virtuoso business unit.
'By extending the capabilities of the Virtuoso platform and teaming with recognised industry leaders, we are now able to offer a well-integrated platform which in turn will help our customers prevent expensive respins and achieve a quicker time to market'.
Cadence will provide access to the wireless design capabilities through customer workshops and downloadable flow kits.
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