Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter RTL Compiler
Edited by the Electronicstalk Editorial Team on 21 December 2004
Compiler cuts SoC power
and area for Oki
Oki has successfully taped out a chip for its uPlat SoC design platform with the new low-power capability of Cadence Encounter RTL Compiler synthesis
With Encounter RTL Compiler, Oki reduced power by 45% and area by 12%. Designed to boost quality of silicon (QoS), Encounter RTL compiler now addresses low-power implementation in a fundamentally new way by extending its multiple-objective global optimisation to dynamic and leakage power optimisation.
This article was originally published on Electronicstalk on 21 December 2004 at 8.00am (UK)
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Compiler improves timing on large ASIC blocks
Renesas Technology Corp has adopted Cadence Encounter RTL Compiler with advanced global synthesis in its ASIC design kits and methodologies for 90nm and below
Speedy synthesis shrinks ASICs and cuts time
Hitachi Communication Technologies has improved synthesis turnaround time by 50 to 70% with Cadence Encounter RTL Compiler global synthesis
This single-pass solution offers improved power, timing and area for higher QoS.
Encounter RTL Compiler's full low-power synthesis solution is unique in its simultaneous optimisation of multiple objectives, yielding a faster route to silicon.
'At Oki, we are using Encounter RTL Compiler for our most important designs, based on our uPlat System LSI design Platform', said Shinji Furuno, a Senior Manager of Silicon Platform Design Department, LSI Design Division at Oki.
Further reading
Comit gains greater access to Cadence technology
Comit Systems has expanded its access to Cadence technology, and has standardised on Encounter RTL Compiler global synthesis, part of the Encounter digital IC design platform
Quality of silicon is key to ARM-based SoCs
Global UniChip Corporation of Taiwan has adopted Cadence Encounter RTL Compiler global synthesis to improve the quality of silicon of its hardened IP
'Encounter RTL Compiler's global synthesis enabled us to substantially reduce power and area, while producing a netlist that sped us through place and route more cleanly than we had experienced with previous technologies'.
Power is a big concern for engineers working on nanometre-scale designs and has become the primary optimisation objective in many projects.
In the digital implementation flow, most of the leakage power optimisation gains are made in the RTL to gate-level synthesis process.
Encounter RTL Compiler's unique, single-pass approach to power, speed and area means higher QoS and a simplified design flow.
QoS measures a design's physical characteristics using wires in terms of improved area utilisation, higher performance and lower power consumption.
Through this, trial and error through multiple runs and multiple tools is substantially reduced.
'We are pleased that such an important customer as Oki has greatly enhanced its low-power design capability with Encounter RTL Compiler', said Chi-Ping Hsu, Corporate Vice President at Cadence.
'With our new global synthesis technology, Cadence delivered improved QoS with faster runtime and higher capacity'.
'This leveraged the advantages of Oki's uPlat integration platform and design environment for improved SoC quality'.
Encounter RTL Compiler includes a unique set of global focus algorithms to maximise the performance of today's most challenging low-power designs.
It works with existing design flows to increase chip performance, decrease design times, and provide the highest QoS.
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