Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Conformal 5.0
Edited by the Electronicstalk Editorial Team on 18 November 2004
Improved verification boosts tapeout confidence
Cadence Design Systems has made substantial enhancements to its market-leading Encounter Conformal technology
Cadence Design Systems has announced substantial enhancements to its market-leading Encounter Conformal technology. Encounter Conformal 5.0 helps customers with enhanced verification capability to insure that the tapeout accurately reflects design intent. Important new capabilities in Conformal 5.0 include, FPGA support, clock domain checking and advanced datapath verification.
This article was originally published on Electronicstalk on 18 November 2004 at 8.00am (UK)
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Conformal technology now extends equivalency checking to FPGA prototypes through the Synplicity design flow to Xilinx devices, with support of Altera devices to follow.
The product also addresses the rapid increase in the number and complexity of clock domains with formal verification of clock domain crossings.
This release of Conformal features SystemVerilog support, complex datapath verification enhancements, and across-the-board equivalence checking capacity and performance improvements.
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"Conformal is the only solution that can prove that our FPGA prototype netlist is functionally identical to our high-end ASIC production design", said Ulrich Hummel, Manager CAD/CAE at Micronas.
"Its ability to verify FPGA synthesis and place and route, along with its extensive debug and ease-of-use features, makes Conformal a required formal verification technology in our FPGA design flow".
"The additional capability of Conformal technology to formally verify our complex clock domain crossing functionality has been beneficial to us", said Hiroshi Furukawa, Assistant Manager 3rd System-on-a-Chip Design Group, System-on-a-Chip Design Division, NEC Micro Systems.
"Simulation is not well suited for this type of verification, and now we are able to exhaustively verify that our clock domains have been correctly implemented".
Conformal technology checks the functional equivalence of versions of a design at various critical stages to help the designer quickly identify and correct errors.
Conformal equivalence checker does not share technology with design tools, ensuring an independent verification audit of the design flow.
This complete, independent verification minimises design respin risk.
With thousands of tapeouts, Conformal technology is the industry's most widely supported equivalence checking solution.
"Conformal 5.0 substantiates the Cadence investment in the Conformal formal verification technology acquired with Verplex last year", said Michael Chang, Vice President of R and D in the Cadence Formal Verification Division.
"We are constantly enhancing this technology to compress the verification cycle and meet the challenges of next-generation designs".
Conformal 5.0, now part of the Cadence Encounter digital IC design platform, is shipping now.
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