Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: IBM-Chartered 90nm reference flow
Edited by the Electronicstalk Editorial Team on 25 May 2004
Reference flow supports 90nm process
Cadence Design Systems has developed a qualified design reference flow validated as compatible with the IBM-Chartered 90-nanometre process platform
The Cadence reference flow seamlessly integrates intellectual property (IP) developed by Artisan Components. for the IBM-Chartered cross-foundry design enablement programme. Developed in conjunction with IBM, this RTL-to-GDSII reference flow - based on the Cadence Encounter digital IC design platform - is optimised across the front-to-back design chain.
This article was originally published on Electronicstalk on 25 May 2004 at 8.00am (UK)
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It offers chip designers a predictable path for SoC design from RTL to first-pass silicon.
The reference flow incorporates leading Cadence technologies including Encounter RTL compiler global synthesis, Encounter Test solutions, and NanoRoute unified routing and physical optimisation.
"This reference flow is another significant step in the ongoing collaboration between Cadence and IBM.
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Cadence, Chartered and IBM customers will be able to use this reference flow to optimise their design process", said Tom Reeves, Vice President, Semiconductor Products and Solutions, IBM Systems and Technology Group.
"It will enable a faster path to volume silicon using the leading-edge IBM-Chartered 90-nanometre CMOS process technologies".
The joint reference flow uses a wire-centric methodology to address key 90-nanometre SoC issues, including low power design, signal integrity, and design-for-test to provide the highest quality of silicon (QoS).
QoS measures a design's physical characteristics using wires in terms of improved area use, higher performance and lower power consumption.
"The combination of advanced process technology, jointly developed by IBM, Chartered and leading-edge Cadence technologies, allows customers to benefit from improved quality of silicon resulting in reduced area, lower power and better performance", said Lavi Lev, Executive Vice President and General Manager, IC Solutions, Cadence.
"Ultimately, our goal is to provide mutual customers with a predictable path to first silicon".
"The Cadence Encounter platform focuses on some of the more challenging issues with regard to 90-nanometre design, and we're pleased to be collaborating with Cadence as a means for customers to accelerate their path to silicon", said Kevin Meyer, Vice President of Worldwide Marketing and Services at Chartered.
"By leveraging the IBM-Chartered design enablement programme, customers enjoy additional benefits such as design portability and a flexible sourcing model".
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