Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Encounter
Edited by the Electronicstalk Editorial Team on 9 March 2004
Implementation platform speeds
90nm DSP to tapeout
Agilent Technologies has successfully implemented a two-million-plus-gate digital signal processor in 90nm process technology using the Cadence Encounter digital IC implementation platform
The new generation technology behind the Cadence Encounter platform helped the Agilent team complete the aggressive design schedule on time. The Cadence Encounter platform again demonstrates that it provides a rapid route to complex, high-performance SoCs. "We are delighted with the results we achieved with the Cadence Encounter platform.
This article was originally published on Electronicstalk on 9 March 2004 at 8.00am (UK)
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Implementing a 400MHz DSP in 90nm requires cutting edge tools", said Jay McDougal, Microprocessor Design Methodology Programme Manager for Agilent's ASIC Products Division.
"Encounter physical implementation technology combined with great support by Cadence helped us to successfully release this chip on schedule".
For the implementation of this DSP, Agilent used the Cadence SoC Encounter physical implementation tool.
A core technology of the Cadence Encounter platform, the SoC Encounter tool offers a complete digital IC implementation solution for nanometre designs including NanoRoute Ultra for nanometre routing.
The SoC Encounter tool provides a fast route to quality silicon with proven tools and methodologies for implementing exceedingly complex, high-performance chips, like the Agilent DSP.
The SoC Encounter tool replaces traditional linear design flows with a new design strategy that minimises time to wires and full-chip iteration time.
The SoC Encounter physical implementation tool provides a higher level of quality of silicon (QoS) by measuring a design's physical characteristics, in terms of area, performance and power-using wires.
"We are pleased to see Agilent successfully implement a 90 nanometre DSP using the Cadence Encounter platform", said Wei-Jin Dai, Platform Vice President, Digital IC Implementation, Cadence Design Systems.
"Once again, Encounter continues to achieve validation in a leading edge production environment".
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