Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: SignalStorm
Edited by the Electronicstalk Editorial Team on 23 June 2003
Delay models accelerate nanometre signoff
Cadence Design Systems and Silicon Metrics have developed nanometre-ready delay models based on extensions to the Liberty model format
The effective current source models (ECSM) can be created by Silicon Metrics' SiliconSmart library characterisation tool and used by Cadence's nanometre delay calculator SignalStorm, the common delay calculation engine of the Cadence Encounter platform. This announcement is the result of close co-operation between the two companies in establishing the characterisation requirements, model format definitions and model qualification.
This article was originally published on Electronicstalk on 23 June 2003 at 8.00am (UK)
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ECSM models have been shown in customer tests to provide superior accuracy, often within 2% of Spice models, and are particularly well suited to modelling the voltage (IR) drop impact on delay that has a major influence on timing at 180nm and below.
When used by SignalStorm in conjunction with VoltageStorm IR drop analysis and Celtic crosstalk analysis, ECSM models provide the cornerstone of Cadence's electrical signoff flow.
Until now, creating ECSM models required a separate timing characterisation process and a binary format.
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By extending the Liberty format, Cadence and Silicon Metrics have unified timing characterisation into a single step and a single format that can support both table lookup models and the advanced ECSM models.
Customers can now use the power of ECSM models while maintaining a consistent set of timing views.
Furthermore, tools that do not support ECSM models will be able to read and ignore the ECSM extensions without requiring any upgrades.
"As the industry transitions to finer process technologies, the complexities of design and the requirement for delay analysis are increasing dramatically", said Vess Johnson, President and CEO of Silicon Metrics.
"Successful design teams have recognised that the accuracy of the characterisation and models used during timing analysis have a direct impact on the quality of their design, the number of design iterations, and time to market".
"The accuracy of any analysis tool is only as good as the quality of the models they consume; therefore, a key component of the design team's success in performing nanometre signoff is the availability of accurate delay models", said Ping Chao, Senior Vice President and General Manager, Chip Implementation at Cadence.
"By providing Spice-qualified ECSM models, Silicon Metrics' SiliconSmart characterisation and modelling technology becomes an integral part of the Cadence design flow".
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