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Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Incisive verification platform
Edited by the Electronicstalk Editorial Team on 25 February 2003

Accelerated verification for nanometre designs

A new verification platform supports a unified verification methodology for the embedded software, control, datapath and analogue/mixed-signal/RF design domains

The Cadence Incisive verification platform is the first single-kernel verification platform for nanometre-scale designs that supports a unified verification methodology for the embedded software, control, datapath and analogue/mixed-signal/RF design domains. The new platform's unified methodology helps slash testbench development time, verification runtime and debug time, and can compress overall verification time by up to 50%.

This enables a dramatic improvement in time to market for semiconductor customers, and accelerated system design-in of complex ICs for design chain partners.

The Incisive platform provides native support for Verilog, VHDL, SystemC, the SystemC Verification Library, property specification language PSL/Sugar, algorithm development and analogue/mixed signal (AMS).

It includes a unique combination of high-performance capabilities: an extensive transaction-level environment; fast, unified test generation; and acceleration on demand.

Cadence has also developed three new products as part of the platform: Incisive, a simulation-based, digital verification solution; Incisive-XLD, a solution for up to 10 engineers that can enable more than 100 times the performance of simulation-based verification; and Incisive-XLD Base, which includes an accelerator/emulator base unit - hardware that delivers 100 to 10,000 times performance improvement.

The company also said it is extending the Cadence IP Partners Programme to support third-party verification IP for the platform.

"Fragmentation within projects, between projects and within design chains has created slow, grossly inefficient verification methodologies", said Rahul Razdan, Cadence Corporate Vice President and General Manager, Systems Verification Group.

"Success in developing complex designs and nanometer-scale ICs requires phenomenal verification speed and efficiency.

This is made possible only by a unified methodology based on a single-kernel architecture with acceleration on demand.

That's something only the Cadence Incisive platform delivers".

"We selected Incisive after evaluating it in both SystemC and multi-language mode with VHDL", said Frank Ghenassia, System and Architecture Design Flows Manager, Central Research and Development at STMicroelectronics.

Using SystemC transaction-level modelling, we achieved 1000 times greater performance than with RTL simulation, enabling our embedded software teams to validate long before detailed RTL was available.

This saved us critical time and reduced risk in our system design cycle.

This performance increase, combined with native support of VHDL and SystemC in the new, unified platform, ensures consistent hardware and software validation through a reusable, system-level testbench for SystemC and RTL".

"AMS Designer, part of the Incisive platform, allows us to verify our next-generation mixed-signal circuits", said Dwayne Sherrard, MS CAD Manager of AMI Semiconductor.

"By taking advantage of behavioural modelling techniques and by being able to cosimulate our digital and analogue blocks, we can take our mixed-signal designs to fabrication with confidence".

For maximum flexibility and performance, Incisive-XLD delivers acceleration on demand, which gives design teams the runtime option of using up to 10 seats of Incisive, or up to a million gates of acceleration capacity.

The acceleration is hosted on a local or remote multiuser Cadence Palladium accelerator/emulator, which can deliver 100 to 10,000 times the performance of simulation.

This capability allows design and verification teams to work interactively during the day and run up to a billion verification cycles overnight.

The integrated solution is more efficient than others that rely on stand-alone or nonintegrated acceleration/emulation technologies.

"The Incisive platform's acceleration on demand capability utilising Palladium provides unparalleled accessibility, flexibility, and performance for hardware-accelerated verification", said Christopher J Tice, Cadence Senior Vice President and General Manager, Verification Acceleration Group.

"Designers can now access the fastest verification solution in their native environments, while dynamically trading off between simulation and hardware-accelerated verification".

"Being able to check image quality at a high resolution as early as possible in the design process is extremely important for graphics applications", said Patrick Scheer, Validation Manager at Philips SP3D Chip Design.

"Our complex designs require extremely high performance - beyond what simulation alone can offer.

We need a combination of simulation, hardware acceleration and emulation to verify our designs completely.

With Palladium, we were able to easily move design data between NC-Sim software simulation and acceleration, even at the sub-module level.

Moving to hardware acceleration with the same transaction-level testbench we used in simulation reduced our turnaround time from five-and-a-half days to six minutes".

The Incisive verification platform supports a unified verification methodology for all design domains: embedded software, control, data path, and analogue/mixed-signal/RF.

This documented methodology is based on proven technology and techniques.

It supports evolutionary migration from existing verification approaches.

The unified methodology begins with an architecturally accurate, transaction-level functional virtual prototype (FVP).

Transaction-level FVPs can run 100 times or more faster than equivalent RTL, making them ideal for architectural performance analysis, early embedded software verification, and early system design-in.

FVPs also provide a fast, full-chip environment for block-level verification.

Within a domain, the unified methodology supports top-down and bottom-up approaches.

When block-level verification is complete, FVPs serve as the vehicle for integrating verified blocks and running full-chip implementation-level verification with acceleration on demand.

"It is important for our Partners developing ARM core-based SoC designs to visualise and validate the full system very early in the design process", said John Goodenough, Global Methodology Manager at ARM.

"ARM has been working closely with lead EDA partners, including Cadence, to develop SystemC-based transaction-level interfaces and methodology.

These amba compliant transaction interfaces will efficiently support the system-level integration and system-verification needs of developers implementing AMBA technology-based systems".

In support of the unified verification methodology, the newly extended Cadence IP Partners Programme now includes verification IP providers.

The program gives customers access to key verification IP, enabling them to reduce verification time further.

It also supports the industry's broadest range of verification IP technology and is the only program of its kind to address the complete design flow, from system design to system design-in.

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