Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Verification Cockpit
Edited by the Electronicstalk Editorial Team on 28 May 2002
Assertion-based verification finds errors early
Cadence Design Systems has enhanced its Verification Cockpit offering with new assertion-based verification technology supporting the Sugar 2.0 Accellera standard language
Cadence Design Systems has enhanced its Verification Cockpit offering with new assertion-based verification (ABV) technology supporting the Sugar 2.0 Accellera standard language. Cadence has also announced SystemC open language support, for design and verification in its NC-Sim and open-source TestBuilder products.
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These moves demonstrate the company's commitment to improve design productivity through solutions based on industry standards and open interfaces.
"Our ABV capability can help digital design engineers detect and eliminate errors earlier in the verification process", said Rahul Razdan, vice president and general manager of the Cadence System and functional verification Group.
"SystemC support can efficiently bridge the gap between complex system design, and hardware/software implementation and verification".
As part of Verification Cockpit, ABV functionality includes Sugar 2.0 assertion language support, extended transaction-based analysis and debug, and new static-checking capabilities.
This combination enables designers to capture specifications, requirements, and assumptions as assertions; verify them statically using static-check techniques, or dynamically using Cadence' s industry-leading mixed-language simulator, NC-Sim; detect internal errors at or near their source; and record assertion activity as transactions in the same form as those already recorded from TestBuilder, Verilog and VHDL testbenches.
Further reading
Software takes holistic view of PCB design
System interconnect design platform adds new capabilities at all stages of printed-circuit board design
Single simulator covers all IC technologies
End-to-end simulation and verification software for custom IC uses a common database of netlists and models to simulate analogue, RF, memory and mixed-signal designs
Kit cuts the cost of low-power IC design
Design kit enables engineers of different experience levels to adopt advanced low-power techniques with minimal risk and deployment effort
The net result can be efficient, comprehensive transaction-based functional coverage analysis in a unified debug environment.
Available this autumn with ABV capability, Verification Cockpit configurations will vary according to customer needs.
Native support of SystemC in the Cadence NC-Sim simulator will enable designers to mix SystemC, RTL, and analog mixed-signal descriptions.
Designers also can view waveforms and hierarchy; control their C/C++, Verilog and VHDL code; and easily debug in a powerful environment that offers mixed simulation of SystemC, Verilog, Verilog-A, VHDL and VHDL-A open languages.
Cadence supports TestBuilder verification extensions to SystemC 2.0.
These enable designers and verification engineers to write reusable testbenches quickly and concisely at a high level of abstraction in C/C++.
"Cadence is working closely with the SystemC Verification Working Group and has proposed inclusion of verification extensions in SystemC", said Eshel Haritan, engineering group director, Systems and Functional Verification Group at Cadence.
"The ability to verify SystemC transaction-level models and reuse the testbench for RTL verification can speed time to market and eliminate the error-prone task of creating a new RTL testbench".
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